Structured LDPC code decoding method and device for system on explicit memory chip

Abstract

The invention relates to a structured LDPC code decoding method and a device for a system on an explicit memory chip; the method comprises the following steps that: (1)decoding initialization: the initialization process comprises the steps that the LLR is stored to a variable node storage block in a special storage method, the value of an initialization calibration node storage block is 0, and a maximum iteration is preset; (2) iterative process: an iteration counter Iter is started, and iteration operation is carried out; and (3) decoding result outputting: when the iteration counter Iter reaches the maximum iteration and the decoding operation of the last calibration node is completed, decoding is stopped and decoding results are output; and otherwise, go to step (2) to continue the iteration. The decoding device comprises a code rate reconfigurable storage management controller, a decoding controller and a processing array unit. The invention has the advantages of simple and compact structure, low cost, convenient operation, capability of reducing the hardware complexity and supporting various code rate and the like.

Description

technical field [0001] The invention belongs to the field of wireless communication, in particular to the field of channel coding and decoding including Low-Density Parity-Checks Codes (LDPC Codes) in wireless communication. Background technique [0002] Communication standards usually use channel coding and decoding technology to reduce the bit error rate BER (Bit Error Rate) during data transmission. LDPC codes, as a class of linear block error-correcting codes whose performance is close to Shannon's limit, have good application prospects. At present, DVB-S2 (Digital Video Broadcasting-Satellite 2), IEEE 802.11n, IEEE 802.16e and other standards all use LDPC code as their core channel coding technology. [0003] The parity check matrix of the LDPC code is a sparse matrix, and the sparse check matrix can be expressed more intuitively through the Tanner diagram. The Tanner graph representation of any LDPC code contains two types of nodes: variable nodes and check nodes. A...

AI Technical Summary

Problems solved by technology

Theoretically, to implement a decoding device that supports multiple code rates, it is necessary to store the parity check matrix for each code rate. At the same time, due to the different degrees of the check nodes of different code rates, the storage of intermediate decoding results is irregular. Also correspondingly increases the area overhead of the decoding device

[0006] At the same time, another issue that needs to be considered when designing an LDPC code decoding device is the connection mode between the decoding controller and the processing unit array, which is also related to the complexity and area overhead of the decoding device

For example, each check node processing unit or variable node processing unit in the LDPC code decoding device provided by the patent (CN200710044715.7) is matched with its own independent decoding controller, but this distributed control method is complex to implement , the area overhead is large, especially for decoding devices with large code length and high parallelism

Images