vertical device structure

Abstract

The present invention provides a vertical device structure. The present invention relates to vertical transistor devices having rectangular vertical channel strips extending between source and drain regions and their associated methods of formation. In some embodiments, a vertical transistor device includes a source region disposed over a semiconductor substrate. A channel region having one or more vertical channel bars is disposed over the source region. The bottom surface of the one or more vertical channel bars adjoins the source region and has a rectangular shape (ie, a four-sided shape with adjacent sides of different lengths and four right angles). The gate region is located above the source region and adjacent to the vertical channel strips, and the drain region is disposed above the gate region and the vertical channel strips. The rectangular shape of the vertical channel bars provides a vertical device with better performance and cell area density.

Description

technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly, to vertical transistor devices and methods of forming the same. Background technique [0002] Moore's Law states that the number of transistors in an integrated circuit doubles approximately every two years. To realize Moore's Law, the integrated chip industry continues to reduce the size (ie, scale) of integrated chip components. In recent years, however, scaling has become more difficult as the physical limits of the materials used in the fabrication of integrated chips are approached. Therefore, as an alternative to traditional scaling, the semiconductor industry has turned to alternative technologies (eg, FinFETs) to continue to satisfy Moore's Law. [0003] An alternative to conventional silicon planar field effect transistors (FETs) that has recently emerged is nanowire transistor devices. Nanowire transistor devices use one or more nanowir...

AI Technical Summary

Problems solved by technology

In recent years, however, scaling has become more difficult as the physical limits of the materials used in the fabrication of integrated chips are being approached

Images