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Rail-to-rail comparator circuit and method thereof

A comparison circuit, rail-to-rail technology, applied in the field of comparison circuits, can solve the problem of increasing overall power consumption

Active Publication Date: 2016-01-27
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However using a preamplifier will increase the overall power consumption

Method used

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  • Rail-to-rail comparator circuit and method thereof
  • Rail-to-rail comparator circuit and method thereof
  • Rail-to-rail comparator circuit and method thereof

Examples

Experimental program
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Embodiment Construction

[0020] Embodiments of the present invention relate to comparison circuits. While the specification describes several embodiments of the invention, it should be understood that the invention may be practiced in various ways and is not limited to the specific embodiments below or to any particular mode or feature employed by those embodiments. In other embodiments, technical details notified in the art are omitted to avoid obscuring the present invention.

[0021] Information disclosed in this manual: "VDD" indicates a power supply circuit node (or a simple power supply node); the logic signal is a signal of "high" or "low"; when it is called "high", the logic The signal is at a high voltage level equal to the voltage level at the power supply node (disclosed here as VDD); when it is referred to as "low", the logic signal is at a low voltage level equal to the voltage level at the ground node, but It should be understood that, in the information disclosed here, "equal to" is an...

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PUM

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Abstract

A circuit includes a PMOS transistor pair receiving a first voltage at a first circuit node and a second voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit node; and an NMOS transistor pair receiving the third voltage at the third circuit node and the fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage at the second circuit node. The circuit further includes a first voltage-controlled resistor controlled by a first control voltage and a second control voltage in accordance with a clock signal providing a coupling between the third voltage at the third circuit node and the second voltage at the second circuit node; and a second voltage-controlled resistor controlled by the second control voltage and the first control voltage in accordance with the clock signal providing a coupling between the fourth voltage at the fourth circuit node and the first voltage at the first circuit node.

Description

technical field [0001] The present invention relates to a comparison circuit, and further relates to a comparison circuit with high-speed operation and low power consumption. Background technique [0002] Those skilled in the art will be able to understand the terms used in the present invention and the basic concepts of related microelectronics, such as MOS (metal oxide semiconductor) transistors, including NMOS (N-type channel metal oxide semiconductor) transistors and PMOS (P-type channel metal oxide semiconductor) transistors. semiconductor), "gate", "source", "drain", "voltage", "current", "circuit", "circuit node", "power supply", "ground", "rail-to-rail" , "clock", "comparison circuit", "inverter", "pull-up", "pull-down", and "latch". Basic concepts like these terms are obvious from prior art documents such as the textbook, "Analog CMOS Integrated Circuit Design", Behrazavi, McGraw-Hill (ISBN 0-07-118839-8), expressing technology in the art and therefore will not be...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K5/22
CPCH03K5/249H03K5/125H03K17/687
Inventor 林嘉亮
Owner REALTEK SEMICON CORP
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