Multipath check device

Abstract

The invention relates to a multipath check device. The multipath check device comprises M inverters with control bits, and N one-in-M multipath devices. The No. i input ends of the N one-in-M multipath devices are in parallel connection, and then connected to the output end of the No. i inverters with control bits. (N and M are integers, M is the power of two, i equals to integers from 1 to M.) When the control bit is of the first level, the inverters with control bits output a high resistance state. When the No. i control bit is of the second level, the No. i inverter with control bits is opened, and the N one-in-M multipath devices are gated. The multipath check device is applied to an FPGA chip, so as to prevent signals from distortion in remote transmission, enable signal output to be completely linear, and reduce power consumption.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a multiplexer. Background technique [0002] Field-Programmable Gate Array (Field-Programmable GateArray, FPGA), which is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It appeared as a semi-custom circuit in the field of application-specific integrated circuits, which not only solved the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of original programmable device gates. [0003] For the FPGA chip, since 80% of its area is the interconnection structure, the interconnection structure is an important functional module of the FPGA, which plays an important role in realizing circuit functions and improving circuit performance. The interconnect fabric consists of multiplexers, figure 1 The simplified circuit structure diagram of the data channel driving another three multiplexers ...

AI Technical Summary

Problems solved by technology

The more inputs that are turned on, the more fan-outs, and the timing from input to output will vary with the number of fan-outs. When the signal of each fan-out changes from 0 to 1, the PMOS transistor driven by the inverter will work The upper is equivalent to a pull-up resistor, the more the fan-out, the stronger the pull-up resistor connected in parallel, the pull-up resistor will divide the voltage with the parasitic resistance on the metal line before the load, the stronger the pull-up resistor, the longer the signal delay Large, when the pull-up resistance is smaller than the resistance of the metal wire, the signal cannot be transmitted. From one fan-out to 32 fan-outs, the delay value does not change proportionally. The more fan-outs, the greater the delay many

The signal maintains complete linearity, that is, the number of loads is proportional to the delay time. When the delay value is not proportionally changed, it is difficult to maintain complete linearity of the signal output.

[0006] (3) When the number of fan-outs is relatively large, due to the large physical distance between the driver and the load, the resistance of the metal wire is very large, and the pull-up resistor on the load causes the rising and falling edges of the signal to be relatively slow, and the intermediate state The time will increase, and the leakage will increase, resulting in greater power consumption

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