A method of manufacturing a memory

Abstract

The invention discloses a manufacture method of a memory. The manufacture method of the memory has functions of reducing etching amount according to a wet method for preventing an effect to structure of a peripheral device, simplifying manufacture process and reducing cost. The manufacture method comprises the steps of forming the multilayer structure of a unit region and the multilayer structure of a peripheral device region on a substrate; processing the multilayer structure of the peripheral device region for forming a polysilicon gate and a polysilicon gate sidewall; etching the multilayer structure of the unit region for forming a control gate; depositing a sidewall layer on the unit region and the peripheral device region; removing the sidewall layer on the polysilicon gate and source / drain region in the peripheral device region; and forming metal silicide on the polysilicon gate and the source / drain region in the peripheral device region.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a memory. Background technique [0002] In non-volatile memory (NVM), a floating gate (FG) is used to store electrons to achieve a "1" or a "0". Floating gates are usually formed of polysilicon. As the size of flash memory continues to shrink, the length of the floating gate and the width of the active area (AA) also continue to shrink. Therefore, the size and shape of the floating gate and the active region have a great influence on the characteristics of the flash memory. [0003] A non-volatile memory (NVM) generally includes a cell area and a peripheral device area. For non-volatile memory (NVM) with self-aligned floating gates, when the cell size is reduced, because the cell size is very small and the aspect ratio (aspectratio) is relatively high, the cell area often remains in the cell area caused by the subsequent process. Deposits, ...

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Problems solved by technology

[0004] The problems of the prior art are: (1) due to the influence of film instability and voids, it is difficult to completely remove the deposits in the cell area, and if these deposits are not completely removed, the contact stop layer nitridation of the contact hole in the subsequent process will be difficult. Silicon will be deposited on these residual deposits, which will cause problems with contact hole openings

(2) If you want to ensure that the deposit is completely removed in the cell area, you need to increase the amount of etching, but a large amount of wet etching will affect the sidewall structure of peripheral devices, and will also affect related device parameters

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