tft array substrate and display

Abstract

The invention provides a TFT array substrate. The TFT array substrate comprises a substrate body, a plurality of TFTs arranged on the substrate body, a plurality of lines of scanning lines and a plurality of rows of data lines, wherein the line width surfaces of the data lines and / or the scanning lines are arranged aslant relative to the surface of the substrate body. The invention also provides a display with the TFT array substrate. According to the TFT array substrate and the display with the TFT array substrate, stray capacitance caused by intersection of the scanning lines and the data lines is reduced, meanwhile impedance of the scanning lines or the data lines cannot be increased, and various problems caused by impedance increasement are avoided.

Description

technical field [0001] The invention relates to a substrate, in particular to a TFT array substrate and a display with the TFT array substrate. Background technique [0002] The current TFT array substrate generally includes multiple rows and multiple columns of TFTs arranged in a matrix, multiple rows of data lines and multiple rows of scanning lines. Since the data line and the scan line are arranged on different layers, and the data line and the scan line are vertically intersected with an insulating layer disposed therebetween, parasitic capacitance will be generated at the intersection of the data line and the scan line. In the existing design, especially the routing design, it is necessary to consider the influence of the parasitic capacitance caused by the intersection of the data line d and the scan line g, and in addition, the line width should not be too wide in the effective display area to avoid affecting the aperture ratio. Such as figure 1 As shown, in an exi...

AI Technical Summary

Problems solved by technology

In the existing design, especially the wiring design, it is necessary to consider the influence of the parasitic capacitance caused by the intersection of the data line d and the scan line g, and in addition, the line width should not be too wide in the effective display area to avoid affecting the aperture ratio

like figure 1 As shown, in an existing way to reduce the influence of parasitic capacitance, the width of the data line is narrowed at the intersection of the data line d and the scan line g, thereby reducing the overlapping area of ​​the data line d and the scan line g and reducing Parasitic capacitance

Although this method reduces the parasitic capacitance, it will increase the impedance of the data line d and cause the risk of vertical light lines and other risks.

In addition, the narrowing of the width of the data line d will make the RC Delay on the data line d (due to the load of resistance and capacitance, the waveform given by the driver chip, etc. will be distorted to a certain extent after being transmitted through the data line, resulting in a delay) Large, when the RC Delay is particularly serious, it will cause insufficient charging or wrong charging of the pixel electrodes connected to the data lines

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