Self-aligned gate contact structure

Abstract

A method of forming a semiconductor device, the method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source / drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided.

Description

technical field [0001] The present invention relates generally to the field of semiconductor device fabrication, and more particularly, to self-aligned gate contact structures and methods of forming the same. Background technique [0002] The continuous scaling down of the fabrication of complementary metal-oxide-semiconductor (CMOS) transistors has currently led to borderless contacts (also known as self-aligned contacts ( SAC)) development. This is primarily because conventional fabrication processes for S / D contacts have frequently been found to cause problems such as electrical shorting between the gate of the transistor and the S / D, where such electrical shorting can sometimes detract from the performance of the transistor. This is especially true in the case of highly shrinking semiconductor device fabrication where the pitch between a transistor and its neighboring transistors can sometimes become extremely narrow or small. In contrast, borderless or self-aligned co...

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Problems solved by technology

[0005] While the borderless contact process described above prevents shorts between the S / D contacts and the gate, it does not prevent shorts between the gate contacts and the active area of ​​the S / D

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