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Low-power scanning self-test circuit and self-test method

A self-testing circuit, low power consumption technology, applied in the direction of measuring electricity, measuring electrical variables, electronic circuit testing, etc., can solve problems such as energy loss, and achieve the effect of low energy consumption replanting

Active Publication Date: 2017-03-29
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But these methods usually result in more energy consumption due to frequent flip-flop scans
Furthermore, most of the previous methods for determining BIST have not focused on low energy consumption

Method used

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  • Low-power scanning self-test circuit and self-test method

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Embodiment Construction

[0035] The objects and functions of the present invention and methods for achieving the objects and functions will be clarified by referring to the exemplary embodiments. However, the present invention is not limited to the exemplary embodiments disclosed below; it can be implemented in various forms. The essence of the description is only to help those skilled in the relevant art comprehensively understand the specific details of the present invention.

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0037] Through this embodiment, the low-power scanning self-test circuit and the test method provided by the present invention are specifically described. In the low-power scanning self-test circuit in the embodiment, the scan chains under the same scan tree are in the same self-test proces...

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Abstract

The invention provides a low-power scanning self-test circuit which comprises a phase shifter, a linear feedback shift register, and a multi-input characteristic analysis register. The low-power scanning self-test circuit is characterized in that the low-power scanning self-test circuit further comprises a scanning forest structure; the scanning forest structure comprises multiple scanning trees connected with the phase shifter; each scanning tree comprises multiple scanning chains which are all connected to the input end of the same clock signal so that all the scanning chains of the same scanning tree are driven by the same clock signal; the input end of each test enable signal is connected with all the scanning chains so different weights are assigned to all the scanning chains; in the multiple scanning chains of each scanning tree, each pair of triggers of each scanning chain have no common access nodes, and the triggers close to each other between two scanning chains are connected; and the linear feedback shift register includes a register bit used for saving all deterministic test vectors.

Description

technical field [0001] The invention relates to the technical field of microelectronic integration, in particular to a low power consumption scanning self-test circuit and a self-test method. Background technique [0002] As the circuit size increases, the gap between functional and test power consumption becomes larger and larger. With the increase of energy consumption, the problem of chip overheating also appeared. Overheating of the chip will shorten the life of the product. Now some more accurate power models have been proposed. One is a fast simulation method for the external interconnect design of low-power chips, and the other is the stacked IC design for the important TSV modeling / simulation technology for low-power 3D networks. Scan-based self-test methods (BIST) have greater power consumption than deterministic scan tests due to the increased random code switching activity. Therefore, it is very necessary to find an effective low-power self-test method (BIST)....

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2851
Inventor 向东刘博
Owner TSINGHUA UNIV
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