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Signal processing circuit

A signal processing circuit and signal technology, applied in the direction of electrical digital data processing, electrical components, analog-to-digital converters, etc., can solve problems such as inaccessible data and unreliable data

Active Publication Date: 2017-04-05
YOKOGAWA ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, if the MPU performs data acquisition processing based on the DRDY signal output from the first ADC, a situation occurs that the MPU acquires unreliable data or cannot acquire the data itself.

Method used

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Examples

Experimental program
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Embodiment Construction

[0050] Embodiments of the present disclosure will be described with reference to the drawings. figure 1 It is a figure which shows the structure of the signal processing circuit 100 of this embodiment. Such as figure 1 As shown, the signal processing circuit 100 has two AD converters (a first ADC 101 and a second ADC 102 ) and an MPU 110 as an arithmetic unit. The first ADC 101 and the second ADC 102 are daisy chained. exist figure 1 In the example shown, the case where two AD converters are daisy-chain-connected is shown for simplicity of explanation.

[0051] Each ADC ( 101 , 102 ) may have the same structure as that of an existing corresponding daisy-chain-connected AD converter. The first ADC 101 and the second ADC 102 have: an analog input terminal (AINP), a digital output terminal (DOUT), a digital input terminal (DIN), a synchronization signal input terminal (SYNC), a serial clock input terminal (SCLK), and Data ready output terminal (DRDY).

[0052] The MPU 11...

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PUM

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Abstract

A signal processing circuit includes: a plurality of daisy chain-connected AD converters each including a data ready output terminal, a synchronizing signal input terminal, and a serial clock input terminal; a calculator connected to the data ready output terminal of any of the AD converters and for outputting a serial clock to the serial clock input terminal of each of the AD converters when a data ready signal is input; and a reset processor included in the calculator and for outputting a synchronizing signal to the synchronizing signal input terminal of each of the AD converters when an output time lag among data ready signals from each of the AD converters is detected for a predetermined number of times.

Description

technical field [0001] The present disclosure relates to signal processing circuits. Background technique [0002] AD converters compatible with daisy-chain connection have already been put into practical use. Such converters are described in, for example, the following documents. [0003] “Texas Instruments Incorporated, 24-Bit, Wide Bandwidth Analog-to-Digital Converter ADS1271 Data sheet Rev.B, November 2004-Revised October 2007, p.24, Search on August 18, 2015, Internet (URL: http: / / www.tij .co.jp / jp / lit / ds / symlink / ads1271.pdf)” [0004] Figure 7 A signal processing circuit 500 including daisy-chain-connected AD converters is shown. It is assumed that each AD converter is required to perform digital conversion at the same timing in the signal processing circuit 500 . [0005] exist Figure 7 In the example, 3 AD converters (1st ADC, 2nd ADC, 3rd ADC) are daisy-chained. The MPU imports serial digital data. A serial interface for converting a plurality of analog dat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12
CPCH03M1/123G06F13/4256H03M1/12G06F13/4247
Inventor 岩下淳一
Owner YOKOGAWA ELECTRIC CORP