A polyphase parallel dcdc circuit and its chip structure

Abstract

The application provides a multi-phase parallel DCDC circuit and its chip structure, which are used to reduce the output parasitics of the EA unit and COMP of the loop operational amplifier, thereby increasing the loop bandwidth and speeding up the transient response. The multi-phase parallel DCDC circuit in the embodiment of the present application includes: a loop operational amplifier EA unit, N output stage circuit units and M drive units, wherein one drive unit corresponds to at least one output stage circuit unit, and the output stage circuit unit includes COMP and Power stage circuit, N is an integer greater than or equal to 2, M is an integer less than or equal to N; the output end of the loop operational amplifier EA unit is connected to the input end of the drive unit; the output end of the drive unit is connected to the corresponding output stage circuit unit The input terminal of COMP is connected, the output terminal of COMP is connected with the input terminal of the power stage circuit in the same output stage circuit unit; the input terminal of the loop operational amplifier EA unit is connected with the output terminals of all power stage circuits.

Description

technical field [0001] The present application relates to the field of circuits, in particular to a multiphase parallel DCDC circuit and its chip structure. Background technique [0002] With the rapid development of consumer electronic products, the demand and performance requirements for the integrated voltage regulator (Integrated Voltage Regulator, IVR) in the power management integrated circuit (Power Management Integrated Circuit, PMIC) in electronic products are also getting higher and higher. Higher requirements are also put forward for the output load capacity of the IVR. The mainstream trend is to improve the load capacity through multi-phase parallel DCDC circuits. At the same time, the IVR is required to respond as quickly as possible to the transient jump of the output load. A common method is to increase the switching frequency of the IVR or increase the loop bandwidth. [0003] For scenarios where the output load capacity of the IVR is required to reach tens ...

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Problems solved by technology

[0005] figure 2 In the scheme, according to a die size of 4mm*4mm, it means that the trace of VEAOUT needs to be at least 8mm long. For the output of EA, the longer the layout trace, the greater the parasitic capacitance and resistance on it. The lower the parasitic pole comes, the lower the frequency will be, which has a great impact on the design of high loop bandwidth, which will eventually lead to the deterioration of the transient response of the loop.

Especially when the number of phases connected in parallel is larger, the area of ​​die is larger, and the trace length and parasitic of EA will increase.

image 3 In the scheme, according to a die size of 4mm*4mm, it means that each output trace of COMP needs to be at least 2mm long. For the output of COMP, the longer the layout trace, the greater the parasitic capacitance and resistance on it. , the lower the frequency of the parasitic pole will be, which will have a great impact on the delay of the loop, resulting in the increase of overshoot or undershoot in the transient response, and finally lead to the deterioration of the transient response of the loop

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