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Method and system for automatically optimizing system-on-chip hierarchical module layout

A system-on-chip, automatic optimization technology, applied in data processing applications, forecasting, computing, etc., can solve problems such as unused area and chip area waste, and achieve the effect of eliminating blank space, reducing costs, and improving effective utilization

Active Publication Date: 2020-08-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention provides a method and system for automatically optimizing the hierarchical module layout of a system on a chip, which solves the problem of unnecessary chip area waste caused by unused areas in the prior art for SOC hierarchical module layout

Method used

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  • Method and system for automatically optimizing system-on-chip hierarchical module layout
  • Method and system for automatically optimizing system-on-chip hierarchical module layout
  • Method and system for automatically optimizing system-on-chip hierarchical module layout

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0096] In this example, if Figure 6 As shown, a method for automatically optimizing the SOC hierarchical module layout specifically includes the following steps:

[0097] 1. Read in the layout of circuit module A and its sub-modules and the design constraints of each sub-module;

[0098] 2. Search for a blank space FS on the layout of the circuit module A to form a queue QFS;

[0099] 3. If the above-mentioned queue QFS is empty, turn to step 10 to end the layout optimization of circuit module A, otherwise turn to step 4;

[0100] 4. Select the blank space FSi from the above-mentioned queue QFS;

[0101] 5. Search for the submodule Ai that causes the empty space FSi;

[0102] 6. Automatically adjust the geometric constraints of sub-module Ai according to the blank space FSi caused by sub-module Ai in module A;

[0103] 7. Rearrange the submodule Ai under the new geometric constraints;

[0104] 8. Delete FSi in the empty space queue QFS;

[0105] 9. Re-layout circuit mod...

Embodiment 2

[0108] In this example, if Figure 7 As shown, the difference from Embodiment 1 is that step 3 is added to sort the blank spaces in the QFS from large to small, and step 5 is to select the largest blank space FSi from the above-mentioned queue QFS, an automatic optimization of SOC hierarchy The module layout method specifically includes the following steps:

[0109] 1. Read in the layout of circuit module A and its sub-modules and the design constraints of each sub-module;

[0110] 2. Search for a blank space FS on the layout of the circuit module A to form a queue QFS;

[0111] 3. Sort the blank spaces in the blank space queue QFS in descending order;

[0112] 4. If the above-mentioned queue QFS is empty, turn to step 11 to end the layout optimization of circuit module A, otherwise turn to step 5;

[0113] 5. Select the largest blank space FSi from the above queue QFS;

[0114] 6. Search for the submodule Ai that causes the blank space FSi;

[0115] 7. Automatically adju...

Embodiment 3

[0121] In this example, if Figure 8 As shown, the difference from Embodiment 1 is that step 3 is added to filter out the blank space with a negligible area in the queue QFS. A method for automatically optimizing the SOC hierarchical module layout specifically includes the following steps:

[0122] 1. Read in the layout of circuit module A and its sub-modules and the design constraints of each sub-module;

[0123] 2. Search for a blank space FS on the layout of the circuit module A to form a queue QFS;

[0124] 3. Filter out the blank space with negligible size in the queue QFS;

[0125] 4. If the above-mentioned queue QFS is empty, then turn to step 11 to end the layout optimization of circuit module A, otherwise turn to step 5;

[0126] 5. Select the blank space FSi from the above-mentioned queue QFS;

[0127] 6. Search for the submodule Ai that causes the blank space FSi;

[0128] 7. Automatically adjust the geometric constraints of sub-module Ai according to the area w...

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Abstract

The invention provides a method and system for automatically optimizing system-on-chip hierarchical module layout. The method comprises steps that (1), a to-be-optimized circuit module, layout of each sub module of the circuit module and geometrical constraints of each sub module are read in; (2), each blank space of each sub module caused by layout carried out according to the geometrical constraints is searched; (3), sub modules causing the blank spaces are searched, and the sub modules are taken as to-be-adjusted sub modules; (4), geometrical constraints of the to-be-adjusted sub modules are adjusted, layout of the to-be-adjusted sub modules under geometrical constraints after adjustment is carried out, geometrical dimensions of the to-be-adjusted sub modules after adjustment can be acquired, and the blank spaces caused by the to-be-adjusted sub modules are removed; and (5), the to-be-optimized circuit module is re-optimized according to the geometrical dimensions of the to-be-adjusted sub modules after adjustment, the steps (1)-(5) are repeated till all the blank spaces are eliminated. The method is advantaged in that a problem of the blank spaces in layout of the module caused by the improper geometrical constraints of the sub modules can be solved, so an effective utilization rate of a chip area can be improved, and cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method and system for automatically optimizing the hierarchical module layout of a system on chip. Background technique [0002] System On Chip (SOC) design technology began in the mid-1990s. With the development of semiconductor process technology, integrated circuit IC designers can integrate more and more complex functions into a single silicon chip. SOC is exactly It is produced under the general direction of IC to integrated system IS transformation. Since SOC can make full use of the existing design accumulation and significantly improve the design capability of Application Specific Integrated Circuit (ASIC), it develops very rapidly and has attracted the attention of the industry and academia. [0003] In the hierarchical design process of integrated circuit system-on-chip (SOC), automatic layout realizes the layout from bottom to top in the hierarchy, and the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06Q10/04G06F30/30
CPCG06F30/30G06Q10/043
Inventor 吴玉平陈岚张学连
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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