High-speed dynamic loading device and method of multiple FPGA based on Ethernet

Abstract

The invention discloses a high-speed dynamic loading device and method of multiple FPGA based on Ethernet, and relates to the technical field of configuration file loading of programmable controllers. The high-speed dynamic loading device and method of the multiple FPGA based on the Ethernet aim at quickly loading configuration files for the multiple FPGA. The technical key points are that the high-speed dynamic loading device comprises a network interface circuit and a configuration-used FPGA, wherein the network interface circuit and the configuration-used FPGA are in a signal connection, the configuration-used FPGA is used for being in a signal connection with each working-used FPGA, receiving first class configuration files sent by the Ethernet through the network interface circuit, and writing the first class configuration files to memories of the corresponding working-used FPGA.

Description

technical field [0001] The invention relates to the technical field of loading configuration files of programmable controllers, in particular to a high-speed loading device and method for configuration files of FPGAs. Background technique [0002] At present, there are a large number of field programmable logic array devices in digital receivers, that is, FPGA devices. Most of the acquisition control and signal processing in digital receivers are completed on FPGA, and FPGA devices are based on RAM. The internal program is automatically cleared. After power-on, the configuration file needs to be loaded from the outside, and then the corresponding action will be executed according to the program in the configuration file. [0003] The common program loading modes of FPGA mainly include: master (active) serial loading mode, slave (slave) serial loading mode, master (active) parallel loading mode, slave (slave) parallel loading mode and JTAG loading mode. The master serial and...

AI Technical Summary

Problems solved by technology

However, the loading configuration files of the latest FPGA devices, such as the Virtex7 series FPGA devices, often have hundreds of megabits. It takes a long time to program the FLASH program using the commonly used USB emulator. If multiple chips in the same JTAG link The configuration file curing of FPGA devices can only be done in a serial manner, which often takes longer to program, and after the program is updated, all FLASH devices need to be re-cured, and the flexibility of use is greatly limited.

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