A Multi-mode Dynamic Loading Method for Heterogeneous Systems

A heterogeneous system, dynamic loading technology, applied in the direction of program loading/starting, program control device, memory address/allocation/relocation, etc., can solve problems such as increasing production cost, and achieve the effect of improved operating distance and strong portability

Active Publication Date: 2017-12-22
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the existing dynamic loading technology requires an additional control chip, which increases the production cost

Method used

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  • A Multi-mode Dynamic Loading Method for Heterogeneous Systems
  • A Multi-mode Dynamic Loading Method for Heterogeneous Systems
  • A Multi-mode Dynamic Loading Method for Heterogeneous Systems

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Embodiment Construction

[0018] The present invention will be further described below in conjunction with accompanying drawing:

[0019] refer to figure 1 , is a schematic diagram of the overall structure of the heterogeneous system of the present invention. The heterogeneous system is electrically connected with a host computer, and the host computer forms a two-way communication connection with the DSP; specifically, the host computer is connected with the DSP through a network cable, an RJ-45 network port, and a high-speed serial interface SGMII. In the embodiment of the present invention, the heterogeneous system includes DSP, FPGA, first Flash memory, and second Flash memory, and the DSP is connected to the first FLASH memory through the SPI bus, wherein the chip select signal of the first FLASH memory is connected to the The first chip select signal of the SPI interface of the DSP; the clock signal of the SPI interface of the DSP is connected to the signal input terminal of the driver chip SN74...

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Abstract

The invention belongs to the technical field of hardware data loading, and in particular relates to a multi-mode dynamic loading method of a heterogeneous system. The specific steps are: when the DSP needs to load the program, the host computer sends the DSP program data to the DSP; the DSP sends the first end sign to the host computer; after the host computer receives the first end sign, it sends the first Flash memory write to the DSP. Command: DSP writes the DSP program data in the DDR3 memory into the first Flash memory according to the first Flash memory write command received; DSP is powered on again to complete the loading of the DSP program data. When the FPGA needs to load the program, the upper computer sends the FPGA program data to the DSP; the DSP sends the third end sign to the upper computer; after receiving the third end sign, the upper computer sends the second Flash memory write command to the DSP; The second Flash memory write command of the second Flash memory is used to write the DSP program data in the DDR3 memory into the second Flash memory; the FPGA is reloaded to complete the loading of the FPGA program data.

Description

technical field [0001] The invention belongs to the technical field of hardware data loading, and in particular relates to a multi-mode dynamic loading method of a heterogeneous system. Background technique [0002] Under the condition of normal operation of a large-scale processor system, due to the limitation of packing or working environment of the board, the board in the chassis usually cannot optimize and upgrade the program through the JTAG interface. Dynamic loading technology in signal processing is a solution to this problem. However, an additional control chip is required in the existing dynamic loading technology, which increases the production cost. At the same time, most of the prior art implements the loading function for a processor chip on the board. Contents of the invention [0003] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art, and propose a multi-mode dynamic loading method for a heterogeneous sys...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445G06F12/02
Inventor 全英汇宋亚坪李亚超王金龙肖川江施佳刚
Owner XIDIAN UNIV
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