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Phase-locked loop, display including same, and method for operating same

A technology of phase-locked loop and inverter, applied in the field of phase-locked loop

Pending Publication Date: 2017-07-18
SAMSUNG DISPLAY CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The complexity of the frequency divider, its power cost, and the necessity of a sigma-delta modulator may be drawbacks of this approach

Method used

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  • Phase-locked loop, display including same, and method for operating same
  • Phase-locked loop, display including same, and method for operating same
  • Phase-locked loop, display including same, and method for operating same

Examples

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Embodiment Construction

[0036] The detailed description set forth below in connection with the accompanying drawings is intended to describe exemplary embodiments of a fractional PLL using a linear PFD with adjustable delay provided in accordance with the present invention and is not intended to represent the only forms in which the invention may be constructed or utilized. The description sets forth the features of the invention in conjunction with the illustrated embodiments. It is to be understood, however, that the same or equivalent functions and structures may be achieved by different embodiments which are also intended to be included within the spirit and scope of the present invention. Like reference numbers are intended to refer to like elements or features as indicated elsewhere herein.

[0037] Embodiments of the present invention address a phase-locked loop (PLL) that is architecturally similar to an integer-N PLL, so the dual-mode divider and associated sigma-delta modulator loop may be ...

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PUM

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Abstract

The invention discloses a phase-locked loop, a display including the same, and a method for operating the same. The phase-locked loop includes a voltage-controlled oscillator having: a control input, and a clock output; and a phase frequency detector having: a reference clock input, a feedback clock input, an up output configured to be either in a set state or a reset state, and a down output configured to be either in a set state or a reset state. The up output and the down output are connected to the control input. The clock output is connected to the feedback clock input. The phase frequency detector includes an adjustable delay block configured to delay, by an adjustable delay time: a transition of the up output from the set state to the reset state, and a transition of the down output from the set state to the reset state.

Description

technical field [0001] One or more aspects of embodiments in accordance with the present invention relate to phase locked loops, and more particularly, to fractional frequency phase locked loops including a frequency phase detector with variable delay. Background technique [0002] In any communication application, a clock signal may be required. Such a signal can be generated from a reference frequency using a phase locked loop (PLL). The relationship between the frequency of the incoming reference clock and the frequency of the output of the PLL can be determined by the division ratio of the frequency divider in the feedback path of the PLL. In an integer-N PLL, the output frequency is an integer multiple of the reference frequency. In such a PLL, the resolution of the output frequency may be limited to N times the resolution of the reference frequency. In some applications, it may be desirable to achieve a finer resolution. One approach uses a fractional-N PLL, where ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/18
CPCH03L7/18H03L7/087H03L7/089H03L7/16H03K5/131H03K2005/00058H03L7/0814H03L7/099H03D13/004H03L7/0891H03L7/091H03L7/093H03L7/1974
Inventor M·赫克马特亚利尔·卡迈利
Owner SAMSUNG DISPLAY CO LTD