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chip packaging

A chip packaging and semiconductor tube technology, applied in the field of chip packaging structure and its formation

Active Publication Date: 2021-07-16
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These newer semiconductor die packaging technologies face process challenges

Method used

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Embodiment Construction

[0063] Many different implementation methods or examples are disclosed below to implement different features of the embodiments of the present disclosure, and specific elements and embodiments of their arrangement are described below to illustrate the embodiments of the present disclosure. Of course, these embodiments are used for illustration only, and should not limit the scope of the embodiments of the present disclosure. For example, it is mentioned in the description that the first feature is formed on the second feature, which includes the embodiment that the first feature is in direct contact with the second feature, and also includes other features between the first feature and the second feature. Embodiments of the features, that is, the first feature is not in direct contact with the second feature. In addition, repeated symbols or signs may be used in different embodiments, and these repetitions are only for simply and clearly describing the embodiments of the prese...

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Abstract

Embodiments of the disclosure provide a chip packaging structure and a method for forming the same. A chip package includes a semiconductor die with conductive features, and a protective layer surrounds the semiconductor die. The chip package also includes a dielectric layer overlying the semiconductor die and protective layer, and partially covering the conductive features. The conductive features are exposed from the protection layer and the dielectric layer. The chip package also includes a conductive layer that penetrates the dielectric layer and is electrically connected to the conductive features of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion exposed from the dielectric layer, and the surface roughness of the second portion is greater than that of the first portion.

Description

technical field [0001] Embodiments of the disclosure relate to semiconductor integrated circuits, in particular to a chip package structure with better electrical connections and a method for forming the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Semiconductor manufacturing processes continue to advance, resulting in finer features and / or higher levels of integration in semiconductor devices. Functional density (ie, the number of interconnected components per chip area) generally increases as feature size (ie, the smallest device that can be made by a manufacturing process) shrinks. This miniaturization process generally offers the benefits of increased production efficiency and reduced associated costs. [0003] Chip packaging not only protects semiconductor devices from environmental pollutants, but also provides a connection interface for the semiconductor devices packaged therein. A small packag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498
CPCH01L23/49811H01L23/49838H01L2224/18H01L23/3128H01L21/561H01L21/566H01L21/568H01L24/19H01L21/6835H01L2221/68345H01L2221/68359H01L2221/68372H01L2221/68381H01L2224/04105H01L2224/12105H01L2224/32225H01L2224/73267H01L2224/97H01L23/49816H01L23/5389H01L23/5384H01L21/486H01L24/16H01L2224/16227H01L24/81H01L2224/2919H01L2224/83101H01L24/29H01L24/32H01L2224/92244H01L2224/83005H01L24/20H01L24/97H01L24/83H01L24/13H01L2224/131H01L2224/83H01L2924/00014H01L2924/0001H01L2924/014H01L23/5386H01L23/5383H01L21/4857H01L24/04
Inventor 张志鸿郭庭豪
Owner TAIWAN SEMICON MFG CO LTD