Verification method of LPC slave device and LPC master device with few-pin interface
A technology of master equipment and equipment, applied in the direction of digital data authentication, instrument, calculation, etc., can solve the problem of not being able to verify the LPC master equipment function verification model and so on
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[0025] figure 1 A schematic diagram of connection between a Low Pin Count (LPC for short) slave device and an LPC master device provided for the embodiment of the present invention. The embodiment of the present invention provides an LPC slave device verification model for a verification model that does not have the IO, MEMORY and FIRMWARE MEMORY functions of LPC in the prior art. The LPC slave device verification model is specifically a function or module of the LPC slave device, that is, the LPC slave device device includes the LPC slave device verification model, as figure 1 As shown, LPC slave device 9 includes LPC slave device verification model 10, LPC slave device verification model 10 includes monitor 11 and driver 12, LPC slave device 9 and LPC master device 14 are connected by LPC bus 13, and LPC slave device 9 and The LPC master device 14 communicates through the LPC bus 13 , and the monitor 11 is used to monitor the signals on the LPC bus 13 . When the monitor 11...
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