A medium-to-high-speed data transmission readout circuit and readout channel used in cmos image sensors

Abstract

The invention relates to a high-speed data readout circuit used in a CMOS image sensor. The circuit is used for sampling and holding, AD conversion, and high-speed interface output of the voltage output by a photosensitive array, and is suitable for high frame rates using column-level ADCs. CMOS image sensor. The high-speed data transmission circuit is connected behind each column of pixels, and is composed of a sample and hold circuit, a column ADC circuit, and a column LVDS output circuit. The circuit performs analog-to-digital conversion on the reset signal and photo-generated signal output by each column of pixels through the pipeline sampling and holding circuit and the column ADC circuit, and then outputs it to the column LVDS circuit through the pipeline type latch and hold circuit to realize high-speed data transmission. According to the method of the invention, high-speed data transmission of various area arrays can be realized, and the circuit scale is small.

Description

technical field [0001] The invention relates to the field of CMOS image sensors, in particular to a medium-to-high-speed data transmission readout circuit used in CMOS image sensors, which is suitable for adopting a column-level ADC circuit structure, and effectively improves the data transmission rate on the basis of ensuring AD conversion accuracy. Background technique [0002] A CMOS (Complementary Metal Oxide Semiconductor) image sensor generally includes a photosensitive pixel array, a row and column decoding circuit, a readout circuit, and the like. The photosensitive pixel array converts the optical signal into an electrical signal, the row / column decoding circuit completes the addressing of the pixels in the region of interest in the pixel array, and the readout circuit reads out and processes the photogenerated signal of the addressed pixel. [0003] CMOS image sensors have two exposure methods: rolling exposure and global exposure. 4T rolling exposure pixels can r...

AI Technical Summary

Problems solved by technology

Chip-level ADC integrates the core device and a single ADC module on one chip. This structure occupies a small area and has a high pixel fill factor, but it consumes high power and is not processed in parallel, which requires high conversion speed of the ADC.

Pixel-level ADC means that each pixel or several pixels share one ADC, the sampling is completely parallel, the signal-to-noise ratio is high, the ADC speed requirement is low, and the power consumption is small, but its fill factor is low, and the dark current and crosstalk between pixels are affected Big

Images