SIMD instruction execution method, apparatus, and processor

Abstract

The invention provides a SIMD instruction execution method, device and processor. The method comprises: if the bit widths of the data units of all source operands participating in the instruction operation and the data units of the target operand are identical, When the instruction is run on a machine with different register widths, the instruction operates on all data units divided by the sourceoperand register and the target operand register according to the bit widths of the data units of the instruction. The invention can only consume less instruction coding for instruction expansion whenthe register bit width is expanded, effectively saves instruction coding space, and can be compatible with programs developed for low bit width processors.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a SIMD instruction execution method, device and processor. Background technique [0002] The SIMD (Single Instruction Multiple Data, Single Instruction Multiple Operand) instruction is a hot spot in the development of computer ISA (Instruction Set Architecture, Instruction Set Architecture) in recent years. SIMD is a set of instructions that can copy multiple operands and pack them in large registers. The characteristic of instruction operation is that parallel operations on multiple data can be performed simultaneously in a single instruction. [0003] The SIMD processor can increase the calculation speed by several times or higher by increasing the bit width of the register so that the register contains more data units. At present, when various instruction sets expand the bit width of SIMD registers, they use different instruction codes to define the same operation instructi...

AI Technical Summary

Problems solved by technology

However, the instructions of the RISC (Reduced Instruction Set Computer) architecture are fixed-length, mostly 32 bits, which include register fields, constant fields, and instruction encoding fields, so the instruction encoding space of RISC instructions is limited. The development of the SIMD instruction set in this way will exhaust the instruction encoding space in the RISC architecture and limit the expansion of future instructions.

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