Wet etching method facilitating decrease of etching by-products

Abstract

The invention relates to a wet etching method facilitating decrease of etching by-products. The method includes the steps: providing a tank, and storing etching solution in the tank; providing a flowuniform plate with a plurality of through holes placed in the tank, and dividing space enclosed by the tank along the depth direction of the tank into an upper cavity and a lower cavity; placing a semiconductor structure to be etched into the upper cavity; injecting the etching solution into the lower cavity, enabling the etching solution to flow the flow uniform plate to reach the upper cavity, and performing wet etching on the semiconductor structure to be etched. According to the wet etching method facilitating decrease of the etching by-product, by the aid of the flow uniform plate, the etching solution flowing the flow uniform plate is distributed by the through holes formed in the flow uniform plate, the etching solution entering the upper cavity by the through holes is distributed into multi-strand etching solution, the etching solution stored in the upper cavity are pushed and stirred by the multi-strand etching solution, so that better pushing effects are achieved, and variousions in the etching solution in the tank can be uniformly distributed.

Description

[0001] The invention relates to the field of semiconductor production and preparation, in particular to a wet etching method for reducing etching by-products. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, research on memory devices with a three-dimensional (3D) structure has gradually heated up this year, and integration density is increased by three-dimensionally arranging memory cells on a substrate. [0003] In the manufacturing process of 3D NAND, removing silicon nitride in the gate line is one of the key steps. At present, the silicon nitride ...

AI Technical Summary

Problems solved by technology

However, with the progress of the reaction, the concentration of silicon in different positions in the phosphoric acid box is different, and there is a phenomenon that the local silicon concentration in the phosphoric acid box is too high

If the local silicon concentration in the pho

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