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Adjustable fractional passive inductor based on FPGA (Field Programmable Gate Array)

A fractional-order, gate array technology, applied in the field of adjustable fractional-order passive inductors, can solve problems such as difficulty in order adjustment

Active Publication Date: 2019-09-06
NORTH CHINA ELECTRIC POWER UNIV (BAODING)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Changing the impedance phase angle of CPE requires changing the coating depth, dielectric conductivity or contact area of ​​the porous PMMA film, so order adjustment is difficult

Method used

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  • Adjustable fractional passive inductor based on FPGA (Field Programmable Gate Array)
  • Adjustable fractional passive inductor based on FPGA (Field Programmable Gate Array)
  • Adjustable fractional passive inductor based on FPGA (Field Programmable Gate Array)

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Embodiment Construction

[0050]In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below in conjunction with the drawings in the embodiments of the present invention. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the invention. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0051] Such as figure 1 As shown, the adjustable fractional-order pas...

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Abstract

The invention discloses an adjustable fractional order passive inductor based on a FPGA (Field Programmable Gate Array). The fractional order passive inductor is implemented by the following steps of:S1: enabling a fractional order integral operator to be approximate to an s-domain partial fraction expansion by utilizing a Charef method; S2: implementing s->z conversion by utilizing a backward Euler method so as to obtain an N-order IIR filter of which first-order links are connected in parallel; S3: determining coefficient digits and state variable digits of the filter in a complement-on-twoform; S4: programming by utilizing a Verilog method, and implementing the fractional order integral operator on the FPGA; and S5: setting up a peripheral circuit and driving an analog-to-digital converter and a digital-to-analog converter.

Description

technical field [0001] The invention relates to the technical field of construction of fractional-order elements, in particular to an adjustable fractional-order passive inductance based on a field programmable gate array. Background technique [0002] Capacitors and inductors defined in traditional circuit theory are integer-order components. In the actual situation, there is a certain degree of loss in the device, and the capacitor and the inductor are fractional order components. Fractional components whose absolute value of order is less than 1 are passive components. [0003] At present, the main construction methods of fractional inductors are: partial reactance approximation circuit method, electrochemical method and analog circuit realization method. [0004] The fractional reactance approximation circuit method uses the existing electrical and electronic components (especially integer order passive components, such as resistors, capacitors, etc.) inductance. The...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/07
CPCG05B19/07
Inventor 梁贵书刘坤刘欣
Owner NORTH CHINA ELECTRIC POWER UNIV (BAODING)