TLM microstructure for GPU hardware to generate Mipmap multi-detail-layer texture algorithm

A technology of detail layer and microstructure, applied in the direction of texture/color, processor architecture/configuration, calculation, etc., can solve the problems of difficult verification and debugging, complex logic, etc., to accelerate the efficiency of reading, writing and storage, and speed up the RTL design. development effect

Pending Publication Date: 2020-04-17
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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AI Technical Summary

Problems solved by technology

The logic of GPU chip hardware is complex when implementing detailed algorithms, and it is difficult to verify and debug at the RTL stage

Method used

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  • TLM microstructure for GPU hardware to generate Mipmap multi-detail-layer texture algorithm
  • TLM microstructure for GPU hardware to generate Mipmap multi-detail-layer texture algorithm

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Embodiment

[0044] Below in conjunction with accompanying drawing the present invention is described in further detail, please refer to figure 1 .

[0045] The structure includes a parameter acquisition module 1 , a module 2 for calculating information of each layer and a module 3 for calculating single-depth Mipmap.

[0046] The acquisition parameter module 1 will receive and generate the Mipmap control signal, obtain the width, height and depth information of each Mipmap layer, and send the width, height and depth of the Mipmap layer to the calculation module 2 for each layer of information through the TLM interface.

[0047] The module 2 for calculating each layer of information will receive the width, height and depth of the Mipmap layer sent by the acquisition parameter module 1, and calculate the number of tiles in the x direction and the y direction, one-dimensional marks, and the last incomplete tile according to the above information. The mark, as well as the Mipmap depth value ...

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Abstract

The invention relates to the technical field of computer hardware modeling, in particular to a TLM microstructure oriented for a GPU hardware to generate a Mipmap multi-detail-layer texture algorithm.The TLM microstructure comprises a parameter acquisition module 1, an each layer information calculation module 2 and a single depth Mipmap calculation module 3 which are connected in sequence; the single depth Mipmap calculation module 3 comprises a tile row Mipmap calculation sub-module 31 and a tile row Mipmap collection sub-module 32; and the tile row Mipmap calculation sub-module 31 comprises a Mipmap calculation unit 311 of a tile. According to the microstructure, the function and the implementation structure of generating the Mipmap multi-detail-layer texture algorithm based on the TLMmodel are achieved, the problem in algorithm function verification of generating the Mipmap multi-detail-layer texture TLM microstructure for GPU hardware is solved, and RTL design and development are effectively accelerated.

Description

technical field [0001] The invention relates to the technical field of computer hardware modeling, in particular to a TLM microstructure for generating Mipmap multi-detail layer texture algorithms for GPU hardware. Background technique [0002] In the design and development of a graphics processor chip (hereinafter referred to as GPU), the correctness and efficiency of algorithms are important factors that determine the function and performance of the GPU. In order to improve performance, the GPU uses tiles (4x4 pixels) as the unit when storing / reading texture data. In order to unify the read and write interfaces, the calculation of Mipmap is also based on tiles (4x4 pixels). How to comprehensively consider one-dimensional, two-dimensional, three-dimensional texture processing, as well as classification of various edge cases, and an algorithm structure suitable for hardware implementation is a technical problem that needs to be solved urgently. GPU chip hardware has complex...

Claims

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Application Information

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IPC IPC(8): G06T1/20G06T11/00G06T15/04
CPCG06T1/20G06T11/001G06T15/04Y02D10/00
Inventor 陈佳蔡叶芳赵彬姜丽云张少锋吴晓成
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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