A gtx codeless transmission method and device

A transmission method and transmission device technology, applied in the field of communication, can solve problems such as design difficulty, design cost, transmission and DC bias, and achieve the effects of solving clock transmission and DC bias, reducing link overhead, and improving transmission efficiency

Active Publication Date: 2022-02-18
HUNAN MAXWELL ELECTRONICS TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the deficiencies of the prior art, provide a GTX codeless transmission method and device, solve the problems of design difficulty and design cost proposed in the background technology, and directly shield the line coder / decoder module at the bottom layer , a scrambling module is implemented at the data sending end, and a frame synchronization and descrambling module is added at the data receiving end, and the data is scrambled when the data is sent externally, which can well ensure the number of 01 flips in the data, Solve clock routing and DC biasing without adding additional line bandwidth

Method used

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  • A gtx codeless transmission method and device
  • A gtx codeless transmission method and device
  • A gtx codeless transmission method and device

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Embodiment 1

[0056] Such as figure 1 , shown in 2; use external data scrambling to replace the GTX internal line codec, and turn off the line codec in the GTX transceiver settings. The data to be sent is sent to the GTX send FIFO after passing through the parallel scrambling module, and the received data is directly converted to parallel without going through a linear decoder. After converting to parallel data, the data is synchronized in parallel through the parallel frame synchronization module, and the synchronized data is then descrambled. The original data can be recovered.

[0057] The parallel scrambling module generates scrambling code data according to the specified primitive polynomial, and then XORs the scrambling code data and the data to be sent except the frame header one by one, so as to complete the scrambling action. Because the scrambling process is to scramble other data except the frame header to ensure that the number of 01 in the statistical sense is consistent, so ...

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Abstract

The invention discloses a GTX codeless transmission method and device, including the steps of using external data scrambling to replace the GTX internal line codec, and turning off the line coder in the GTX transceiver settings, so that the data to be sent is processed in parallel. After being scrambled, it is sent to the GTX transmit FIFO, and the received data is directly converted into parallel without going through a linear decoder; after being converted into parallel data, the data is synchronized in parallel through parallel frame synchronization, and the synchronized data is then descrambled operation, the original data to be sent can be recovered. The present invention directly shields the line encoder / decoder module at the bottom layer, adds a scrambling module at the data sending end, adds a frame synchronization and descrambling module at the data receiving end, and scrambles the data when sending data externally Interference can well guarantee the number of 01 flips in the data, solve the problems of clock transmission and DC bias, and do not need to increase additional line bandwidth.

Description

technical field [0001] The present invention relates to the field of communication technology, and more specifically, to a GTX codeless transmission method and device. Background technique [0002] In the design of the current system-level interconnect rate that has reached Gbps, the advanced high-speed serial technology quickly replaces the traditional parallel technology and becomes the mainstream of the industry. High-speed serial technology can not only bring higher performance, lower cost and more simplified design, overcome the parallel speed bottleneck, but also save I / O resources and make the wiring of printed boards simpler. Therefore, it is more and more widely used in various system designs, including PCs, consumer electronics, mass storage, servers, communication networks, industrial computing and control, test equipment, etc. [0003] At present, mainstream FPGAs integrate GTX transceivers, built-in high-speed serial-to-parallel conversion, clock and data recov...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H04L7/00
CPCH04L1/0033H04L1/0036H04L7/00
Inventor 吕游何峰赵海军
Owner HUNAN MAXWELL ELECTRONICS TECH
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