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Memory interface timing analysis method and system

A memory interface, timing analysis technology, applied in the field of communications, can solve the problem that the eye diagram analysis method cannot adapt to complex eye diagrams

Active Publication Date: 2021-11-26
AMOLOGIC (SHANGHAI) CO LTD
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] Aiming at the problem that existing eye diagram analysis methods cannot adapt to complex eye diagrams, a memory interface timing analysis method and system that can adapt to different eye diagrams and accurately obtain the optimal setting parameters of the interface are now provided

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  • Memory interface timing analysis method and system

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Embodiment Construction

[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work all belong to the protection scope of the present invention.

[0041] Data training (data training) two-dimensional eye diagram acquisition process is: by moving the input reference level of the receiver and the delay of the input and output signals, according to the read and write to judge whether the data is correct, so as to obtain the two-dimensional dot matrix of the signal, Draw an eye diagram based on a 2D dot pattern.

[0042] But the actual signal eye diagram may be very complex, such as: eye collapse, mult...

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Abstract

The invention discloses a memory interface timing sequence analysis method and system, belonging to the technical field of communication. The memory interface timing analysis method and system of the present invention can determine the step offset value according to the standard eye height corresponding to the memory interface; thus, according to the step offset value, the first signal eye diagram can be translated upward and downward, and the adjusted The signal eye diagram is superimposed, and then the second signal eye diagram in the overlapping area is obtained, so as to determine the optimal location information of the memory interface, realize self-adaptation to different eye diagrams, and accurately obtain the optimal location information of the memory interface (optimal setting parameters) the goal of.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a memory interface timing analysis method and system. Background technique [0002] With the technological progress of the times, the current microcomputer system has higher and higher requirements for DDR (Double Data Rate, double data rate) memory interface technology. DDR memory interface standards have gradually evolved from the first generation of DDR, such as: DDR2, DDR3, DDR4, DDR5 (and low-power LP type), etc. Compared with the first generation of DDR memory particles, the speed bandwidth and energy consumption standards have been greatly improved. In order to meet the high performance requirements, the DDR interface has stricter requirements on the eye width and eye quality of the signal eye diagram. Therefore, it is necessary to consider the design of the entire DDR memory interface more comprehensively and fully during the generation process. One of the most ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/01G06F13/16
CPCG06F3/013G06F13/1668
Inventor 叶佳星傅祥欧阳志光
Owner AMOLOGIC (SHANGHAI) CO LTD