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Peaking inductor embedded within t-coil

A peaking inductance and inductor technology, applied in the structural field of peaking inductors and T coils, can solve problems such as intensifying the inefficient use of chip available space

Pending Publication Date: 2020-10-09
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The T-coil and on-chip peaking inductor also have a separate keep out zone, which further exacerbates the inefficient use of available space on the chip

Method used

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  • Peaking inductor embedded within t-coil
  • Peaking inductor embedded within t-coil
  • Peaking inductor embedded within t-coil

Examples

Experimental program
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Embodiment Construction

[0013] Please refer to figure 1 And according to an embodiment of the present invention, the circuit 10 includes a plurality of inductors 12, 14, 16 disposed on a chip, and the chip also includes one or more inductors manufactured by a front-end-of-line (FEOL) process. multiple integrated circuits. Inductors 12, 14, 16 are located within the interconnect structure 30 of the chip ( Figure 2-4 ), the interconnection structure can be formed through a back-end process (BEOL) process. Inductors 12, 14 are included in circuit 10 as connecting components of the T-coil. The turns or windings of the inductors 12, 14 included in the T-coil are stacked with the turns or windings of the inductor 16 in an upright direction, as described later, to provide a composite structure having the windings in a stacked arrangement. The stacked arrangement of the windings of the inductors 12, 14, 16 provides a more compact structure compared to a non-stacked arrangement.

[0014] Terminal 11 of i...

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Abstract

The invention relates to a peaking inductor embedded within a T-coil, and discloses structures including the peaking inductor and the T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. The peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor arestacked in the back-end-of-line interconnect structure with an overlapping arrangement.

Description

technical field [0001] The present invention relates to semiconductor device fabrication and integrated circuits, and more particularly to structures including peaking inductors and T-coils, and methods associated with forming such structures. Background technique [0002] Inductors represent an on-chip passive device commonly used in many types of monolithic integrated circuits designed to operate at high frequencies. The inductor can be fabricated in the metallization level of the back-end-of-line (BEOL) interconnect structure on the chip. An inductor can be characterized by a figure of merit, which is a figure of merit representing a measure of the relationship between energy loss and energy storage. A high value for the figure of merit reflects a low energy loss to the chip's substrate. However, increasing the quality factor comes at the expense of increasing the size of the inductor. The design of an on-chip inductor often has to balance the space occupied by the ind...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522
CPCH01L23/5227H01L23/60H01F17/0013H01F2017/002
Inventor 文卡塔·N·R·法努卡鲁U·K·舒克拉S·托加尔
Owner GLOBALFOUNDRIES U S INC MALTA
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