SoC chip verification test system and method

A verification test and chip technology, which is applied in the field of SoC chip verification test system, can solve problems such as insufficient stability, problems in verification results and test results, etc., to facilitate query and summary, avoid operation result recording errors, and improve stability Effect

Active Publication Date: 2020-10-30
INSPUR BEIJING ELECTRONICS INFORMATION IND
View PDF16 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the stability of the existing verification test platform is insufficient, which may cause problems in verification results and test results

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SoC chip verification test system and method
  • SoC chip verification test system and method
  • SoC chip verification test system and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0030] At present, the stability of the existing verification test platform is insufficient, which may cause problems in the verification results and test results. For this reason, the present application provides a SoC chip verification test solution, which can guarantee the correctness of verification results and test results.

[0031] see figure 1 As shown, the embodiment of the present application discloses the first SoC chip verification test system, including: a control termi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses an SoC chip verification test system and method. The system comprises a control end and a plurality of verification test platforms connected with the control end, and the control end is used for sending the same control instruction to at least two verification test platforms, so that the at least two verification test platforms verify or test the same function point of theSoC chip to obtain at least two operation results; and the control end is also used for receiving and comparing the at least two operation results to obtain a comparison result, recording the comparison result and the at least two operation results into a recursion table of the function points, and storing the recursion table into a database. According to the invention, technicians can conveniently call verification test data for analysis; reliable data support is provided for design, modification and perfection of the SoC chip, operation result recording errors caused by instability of a certain verification test platform can be avoided, system stability is improved, and correctness of verification results and test results is guaranteed.

Description

technical field [0001] The present application relates to the technical field of integrated circuit testing, in particular to a SoC chip verification testing system and method. Background technique [0002] SoC (System on Chip, system-on-chip) is an integrated circuit with a dedicated purpose. After the design of each function point in the SoC is completed, the correctness of these function points needs to be verified. If the correctness of the function point is verified, the stability of the function point in various scenarios is tested. [0003] Usually, the hardware circuit design can be used to realize the verification test platform. Under the control of the host, this verification test platform runs each function point of the SoC chip one by one, and feeds back the running results to the host. However, due to abnormal conditions such as sampling errors in hardware circuits in some special environments, special environments such as: high temperature environment, low tem...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/263
CPCG06F11/2273G06F11/263
Inventor 任智新李仁刚张闯谢志勇孙颉
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products