A kind of DRAM chip three-dimensional integration system and its preparation method
A three-dimensional integration and chip technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as increased process complexity, warpage deformation, and waste of silicon materials
Active Publication Date: 2021-07-06
FUDAN UNIV +1
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Problems solved by technology
The thinning of silicon wafers will undoubtedly increase the complexity of the process, resulting in waste of silicon materials, and it is also prone to warping and deformation problems
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[0020] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0021] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relation...
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The invention discloses a DRAM chip three-dimensional integration system and a preparation method thereof. Several trench structures are etched on the front and back sides of the silicon wafer; then, a TSV structure is etched between the upper and lower opposite trenches for electrical connection; then, a DRAM chip is placed in the trench, and copper-copper The bonding method makes the chips in the vertical direction electrically connected to the TSV structure; finally, rewiring is performed to make the chips in the horizontal direction electrically connected. The invention can make full use of the silicon material, and can avoid problems such as warping and deformation of the adapter plate. In addition, placing the chip in the groove will neither increase the thickness of the overall package, but also protect the chip from external shocks.
Description
technical field [0001] The invention belongs to the field of integrated circuit packaging, and in particular relates to a DRAM chip three-dimensional integration system and a preparation method thereof. Background technique [0002] With the rapid development of integrated circuit technology, microelectronic packaging technology has gradually become the main factor restricting the development of semiconductor technology. In order to realize the high density of electronic packaging, obtain better performance and lower overall cost, technicians have developed a series of advanced packaging technologies. Among them, the three-dimensional system-in-package technology has good electrical performance and high reliability, and can achieve high packaging density at the same time, and is applied to a dynamic random access memory (DRAM) chip system. [0003] Through Silicon Via (TSV) interposer technology is a new technology for interconnection of stacked chips in three-dimensional i...
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IPC IPC(8): H01L23/48H01L25/065H01L21/768H01L21/52
CPCH01L23/481H01L25/0652H01L21/76898H01L21/52H01L2224/16225H10B12/01H10B80/00H01L2225/06572H01L2225/06517H01L2225/06555H01L23/13H01L24/14H01L24/13H01L24/05H01L24/16H01L24/03H01L24/11H10B12/30H01L2224/17104
Inventor 朱宝陈琳孙清清张卫
Owner FUDAN UNIV