D trigger, nonlinear phase detector and data recovery circuit

Abstract

The invention discloses a D trigger , a nonlinear phase detector and a data recovery circuit. The D trigger comprises a current mode latch, a sensitive amplifier and an RS latch which are connected insequence, wherein the current mode latch is low-level effective; a positive-phase input end and a negative-phase input end of the current mode latch are respectively used as a positive-phase input end and a negative-phase input end of the D trigger; a normal-phase output end and a reverse-phase output end of the RS latch are respectively used as a normal-phase output end and a reverse-phase output end of the D trigger; and a clock input end of the current mode latch is connected with a clock input end of a sensitive amplifier and serves as a clock input end of the D trigger. The D trigger isconstructed by combining the current mode latch and the SAFF, so that the circuit not only has the advantages of high input sensitivity, high rejection ratio and the like of a current mode logic circuit, but further has the advantages of low power consumption and full swing of output signals of the SAFF, the sensitivity and the accuracy are effectively improved, and the economic benefit of a product is further improved.

Description

Technical field[0001]This application relates to the technical field of data serial-parallel interface transmission, and in particular to a D flip-flop, a nonlinear phase detector and a data recovery circuit.Background technique[0002]D flip-flops have important applications in ultra-high-speed circuit design, especially in bang-bang phase detectors.[0003]referencefigure 1 ,figure 1 It is a schematic diagram of a D flip-flop used in the prior art.figure 1 The specific shown is a current mode (Current Mode Logic) based D flip-flop with a master-slave structure, referred to as CML DFF, which consists of two high-speed latches, LACH-L is a low-level effective latch LACH-H is a high-level active latch. The circuit load is small, so it needs to output a large drive current to reach the ideal output amplitude, so the power consumption is large.[0004]referencefigure 2 ,figure 2 It is a schematic diagram of another D flip-flop used in the prior art.figure 2 The specific shown is a D flip-flo...

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Problems solved by technology

figure 2 Although the D flip-flop shown has the advantages of fast speed, no need for full-scale input data, full-scale output data, etc., it will cause serious misjudgment when collecting edge information, especially under high temperature conditions. It is more obvious in the low-voltage SS process corner, which makes the sampling point of the clock data collection offset from the center point and increases the bit error rate

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