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A timing analysis method, device, electronic equipment and storage medium

A timing analysis and timing technology, applied in electrical digital data processing, computer-aided design, instruments, etc., can solve the problems of low efficiency of timing analysis and optimization, complex and difficult positioning of key timing modules, etc., to reduce the number of iterations and improve efficiency. Effect

Active Publication Date: 2021-10-12
CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of this, the embodiments of the present invention provide a timing analysis method, device, electronic equipment, and storage medium to solve the problem of complex positioning of the existing timing critical modules, which leads to low efficiency of timing analysis and optimization

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  • A timing analysis method, device, electronic equipment and storage medium
  • A timing analysis method, device, electronic equipment and storage medium
  • A timing analysis method, device, electronic equipment and storage medium

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Embodiment Construction

[0022] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0023] It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0024] First of all, some existing terms in the embodiments of the present disclosure are explained to facilitate the understanding of those skilled in the art.

[0025] The timing path refers to the logic path that the data signal passes through during the propagation of the chip design. Each timing path has a corresponding start point and an end point. The starting point of the timing path is divided into the data input port of the combinational logic unit and the clock input port of the timing unit; the terminati...

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Abstract

The embodiment of the present invention discloses a timing analysis method, device, electronic equipment, and storage medium, which relate to the technical field of chip design and can overcome the drawbacks of low analysis efficiency and difficulty in timing convergence due to difficult positioning of timing key modules. The method includes: calculating the maximum timing violation severity metric value of the timing end / timing start point in multiple timing paths for timing analysis; determining the icon corresponding to the calculated maximum timing violation severity metric value of the timing end point / timing start point Draw information; use a certain icon to draw information, and draw a corresponding icon for identifying the severity of the timing violation for the timing end point / timing start point. The invention is applicable to the sequence analysis scene in chip design, can improve the efficiency of sequence analysis and accelerate the convergence of sequence.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a timing analysis method, device, electronic equipment and storage medium. Background technique [0002] Nowadays, chip technology is developing rapidly, and the designed chips are widely used in various fields such as mobile terminals such as mobile phones, smart homes, and military products. In chip design, the circuit part is usually dominated by synchronous circuits. In order to ensure that the designed chip can work normally, it is necessary to perform timing analysis on the circuit after the chip circuit components are placed. [0003] As an important link in the sequential circuit design process, timing analysis usually refers to: based on specific timing requirements or timing constraints, using a specific timing model to analyze chip circuits. Through timing analysis, it is possible to find timing violation paths and even timing violation critical paths, and then us...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392G06F30/396
CPCG06F30/392G06F30/396
Inventor 石建刚晋大师王毓千
Owner CHENGDU HAIGUANG INTEGRATED CIRCUIT DESIGN CO LTD
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