Method for carrying out process monitoring on reconfigurable FPGA software

Abstract

The invention discloses a method for carrying out process monitoring on reconfigurable FPGA software, and the method comprises the following steps: while carrying out copy monitoring on important internal signals by utilizing a special verification test system of the reconfigurable FPGA software, leading out the important internal signals through FPGA pins, and transmitting the important internal signals from a test board to a main control FPGA board through the FPGA pins to be collected. The special verification test system for the reconfigurable FPGA software comprises a signal transmission layer module; a verification instruction layer module; a verification function layer module; a verification environment layer module; and a verification top layer module.

Description

technical field [0001] The invention relates to the field of computer software verification testing, in particular to a method for process monitoring of reconfigurable FPGA software. Background technique [0002] Field programmable logic device (FPGA) technology has achieved amazing development in the past few decades. The fundamental reason is that FPGA can not only solve the problems of electronic system miniaturization, low power consumption, and high reliability, but also has a short development cycle. , Less investment in developing software, and lower chip prices have prompted FPGAs to increasingly replace ASICs in the market, especially for small-batch and multi-variety products, making FPGAs the first choice. [0003] At present, in response to more and more on-board FPGA software reconfiguration requirements, traditional FPGA verification testing methods cannot meet the verification requirements of reconfigurable FPGA software in terms of verification function test ...

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Problems solved by technology

[0006] The FPGA general verification test system proposed later, although it uses the hierarchical structure, unified test case format and extraction of general base classes to set up, but because its main purpose is to establish a general verification platform, it does not consider that the FPGA software is closely related to the interface protocol , and it is impossible to implement a general verification environment for FPGAs for all types or functions; at the same time, the driver classes in this architecture come from the upper driver layer, and the driver is transmitted by calling the pre-existing driver data. The generation of this method will It brings multiple disadvantages: 1. The pre-compiled driver code library needs a large sample test library, and this library needs to be pre-implemented for all chip types and different functions, and the workload in the background can be imagined. And once there is a verification requirement with special test points such as reconfigurable FPGA software, it can only be added from the top layer of its verification test system, and then called layer by layer, the steps are cumbersome

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