A special verification test system for reconfigurable fpga software

Abstract

The invention discloses a special verification test system for reconfigurable FPGA software, comprising: a signal transfer layer module, the signal transfer layer module provides direct signal interconnection with the reconfigurable FPGA software to be tested, and is verified by the special Accessed by other modules of the test system; the verification instruction layer module, the verification instruction layer module monitors the front-end input and the final output of the reconfigurable target reconfiguration code of the reconfigurable FPGA software, and also monitors the reconfigurable FPGA software. The operation process of the refactored code of the test target is monitored; the verification function layer module compares the output result of the refactored code of the target to be tested with the processing result of the verification platform; the verification environment layer module, the The verification environment layer module registers the use of the scene in the environment layer; and the verification top-level module defines the global top-level file, and constrains the global variable and the working mode of the reconfiguration code of the target to be tested.

Description

technical field [0001] The invention relates to the field of computer software verification test, in particular to a special verification test system based on on-orbit reconfigurable FPGA software. Background technique [0002] Field programmable logic device (FPGA) technology has achieved amazing development in the past few decades. The fundamental reason is that FPGA can not only solve the problems of electronic system miniaturization, low power consumption, and high reliability, but also has a short development cycle. , Less investment in developing software, and lower chip prices have prompted FPGAs to increasingly replace ASICs in the market, especially for small-batch and multi-variety products, making FPGAs the first choice. [0003] At present, in response to more and more on-board FPGA software reconfiguration requirements, traditional FPGA verification testing methods cannot meet the verification requirements of reconfigurable FPGA software in terms of verification...

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Problems solved by technology

[0006] The FPGA general verification test system proposed later, although it uses the hierarchical structure, unified test case format and extraction of general base classes to set up, but because its main purpose is to establish a general verification platform, it does not consider that the FPGA software is closely related to the interface protocol , and it is impossible to implement a general verification environment for FPGAs for all types or functions; at the same time, the driver classes in this architecture come from the upper driver layer, and the driver is transmitted by calling the pre-existing driver data. The generation of this method will It brings multiple disadvantages: 1. The pre-compiled driver code library needs a large sample test library, and this library needs to be pre-implemented for all chip types and different functions, and the workload in the background can be imagined. And once there is a verification requirement with special test points such as reconfigurable FPGA software, it can only be added from the top layer of its verification test system, and then called layer by layer, the steps are cumbersome

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