Unlock instant, AI-driven research and patent intelligence for your innovation.

Erase method for multi-tier 3D memory

A multi-level, memory technology that is used in the memory field to solve problems such as damage

Pending Publication Date: 2021-09-28
MACRONIX INT CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the increased erase voltage will also hold the cells whose threshold voltage is lower than the erase verification voltage, which may cause further damage to these cells whose threshold voltage is lower than the erase verification voltage.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Erase method for multi-tier 3D memory
  • Erase method for multi-tier 3D memory
  • Erase method for multi-tier 3D memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0023] The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanation or definition of this part of the terms shall prevail. Each embodiment of the present disclosure has one or more technical features respectively. On the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments .

[0024] now please refer to figure 1 , which shows a functional block diagram of a three-dimensional memory according to an embodiment of the present disclosure. Suc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

Description

technical field [0001] The invention belongs to the technical field of memory, and relates to a method for erasing a multi-tier three-dimensional memory. Background technique [0002] With the increase of memory storage density, three-dimensional (3D) memory has been developed. In a three-dimensional memory, multiple word lines are grouped into multiple tiers, such as double-tier or triple-tier. Each word line can also be called a layer (layer), because these word lines are arranged in a horizontal manner. [0003] When performing an erasing operation on a three-dimensional memory, a block is used as a unit. A block consists of multiple cells. When performing an erase operation, if all cells in the selected block are lower than the erase verify (erase verify) voltage, the selected block is considered to be erased successfully. However, during the erasing process, for the same selected block, the threshold voltage of some cells has been lower than the erase verification v...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
CPCG06F3/0604G06F3/0673G06F3/064G11C16/16G11C16/3445G11C16/08G11C16/0483
Inventor 古绍泓郑致杰程政宪黄昱闳铃木淳弘蔡文哲
Owner MACRONIX INT CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com