Shift register and display driver

Abstract

The invention discloses a shift register and a display driver. The shift register comprises an output adjustment sub-module which outputs a first power supply signal from the output end of the shift register according to the potential of a first node and outputs a first clock signal from the output end of the shift register according to the potential of a second node, a triggering write-in sub-module, and a node adjusting sub-module which is used for adjusting the potential of the first node and comprises a power supply introducing sub-module, a first coupling sub-module and a first adjusting sub-module, wherein the first clock signal comprises a first type level and a second type level, the second clock signal comprises the first type level and the second type level, the moment when the second clock signal jumps to the first type level is within the duration of the second type level of the first clock signal, the first clock signal and the second clock signal have the same period, and the durations of the same type of levels are different. According to the invention, the scanning signal which spans a plurality of line times and is free of trailing can be output.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of shift registers, in particular to a shift register and a display driver. Background technique [0002] The shift register has an important application in the display panel field, and various scanning signals need to be provided for the display panel to drive the pixel circuits in the display panel to work. [0003] However, some new pixel circuits for low refresh rates need to be driven by pulse scanning signals spanning multiple row times, and the existing shift registers cannot output pulse signals that continuously span multiple row times without smearing. Contents of the invention [0004] The invention provides a shift register and a display driver, so that the shift register can output a scanning signal spanning multiple row times without smearing. [0005] In a first aspect, an embodiment of the present invention provides a shift register, and the shift register include...

AI Technical Summary

Problems solved by technology

[0003] However, some new pixel circuits for low refresh rates need to be driven by pulse scanning signals spanning multiple line times, and the existing shift registers cannot output pulse signals that continuously span multiple line times without smearing.

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