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Memory system and operating method thereof

A technology of a memory system and an operation method, applied in the field of memory system and its operation, can solve problems such as an increase in the number of error bits, and achieve the effect of reducing overhead

Inactive Publication Date: 2022-03-15
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this case, if the historical read bias value corresponding to that particular memory block is not optimized, there may be a problem that when the data stored in the corresponding memory block is read, the number of error bits generated increase the amount

Method used

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  • Memory system and operating method thereof
  • Memory system and operating method thereof
  • Memory system and operating method thereof

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Embodiment Construction

[0036] Hereinafter, exemplary embodiments of the present disclosure are described in more detail with reference to the accompanying drawings. Throughout the specification, references to "an embodiment," "another embodiment," etc. are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment. When the term "various embodiments" is used herein, it does not necessarily mean all embodiments.

[0037] figure 1 is a diagram showing a schematic configuration of a memory system 100 based on an exemplary embodiment of the technology of the present disclosure.

[0038] In some embodiments, the memory system 100 may include a memory device 110 configured to store data and a memory controller 120 configured to control the memory device 110 .

[0039] The memory device 110 may include a plurality of memory blocks each including a predetermined number of memory cells for storing data. The memory device 110 may be config...

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Abstract

Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to an exemplary embodiment of the present disclosure, when the number of error bits generated in a first read operation for a first memory block among a plurality of memory blocks is greater than or equal to a first threshold value and less than a second threshold value, the first memory block is read; the memory system may store information on a number of error bits generated in a first read operation in an error bit history set, and may repeat an operation of calibrating a history read bias corresponding to a first memory block during a read operation performed after the first read operation for the first memory block, and stopping until a set termination condition is met.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0117490 filed on September 14, 2020, which is hereby incorporated by reference in its entirety. technical field [0003] Embodiments relate to a memory system and method of operating the same. Background technique [0004] A memory system such as a storage device stores data based on a request from a host such as a computer, a mobile terminal (eg, a smartphone or a tablet), or any of various other electronic devices. The memory system may be a device that stores data on a magnetic disk such as a hard disk drive (HDD), or a device that stores data on a non-volatile devices in sexual memory. [0005] The memory system may further include a memory controller for controlling the memory device. The memory controller may receive commands from the host, and based on the received commands, may operate or control functions for reading data, writing d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26G11C16/34G11C29/42
CPCG11C16/26G11C16/3404G11C29/42G06F11/1048G11C16/08G11C29/18G06F3/0655G06F3/0679G06F3/0604
Inventor 文敏焕
Owner SK HYNIX INC
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