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Process for preparing shallow-channel isolating structure

A technology of isolation structure and manufacturing method, applied in the direction of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of affecting production volume, reducing productivity, slow deposition rate, etc.

Inactive Publication Date: 2005-05-04
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, the high-density chemical vapor deposition method with a high etching / selection ratio has the problem of slow deposition rate. Therefore, although the insulating layer of the shallow trench isolation structure formed by this method can avoid the generation of defect points, it will reduce the productivity. And affect the throughput (Throughput)

Method used

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  • Process for preparing shallow-channel isolating structure
  • Process for preparing shallow-channel isolating structure
  • Process for preparing shallow-channel isolating structure

Examples

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Embodiment Construction

[0036] Figure 2A to Figure 2E It is a schematic cross-sectional view of a manufacturing process of a shallow trench isolation structure according to an embodiment of the present invention.

[0037] First, please refer to Figure 2A 1. A substrate 200 is provided, and a pad oxide layer 202 is formed on the substrate 200, wherein the material of the pad oxide layer 202 is, for example, silicon oxide; the forming method is, for example, a thermal oxidation method. Next, a mask layer 204 is formed on the pad oxide layer 202 . The material of the mask layer 204 is, for example, silicon nitride; the method of forming the mask layer 204 is, for example, chemical vapor deposition.

[0038] Next, please refer to Figure 2B , removing part of the mask layer 204 , the pad oxide layer 202 and the substrate 200 to form the trench 206 . The method for forming the trench 206 is, for example, forming a patterned photoresist layer (not shown) on the mask layer 204 . Then, using the photo...

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PUM

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Abstract

The invention relates to a manufacturing method of a shallow trench isolation structure. The method provides a substrate. First, a pad oxide layer and a mask layer are sequentially formed on the substrate, and then part of the pad oxide layer and the mask are removed. layer and the substrate to form trenches in the substrate. Next, a first-stage insulating layer deposition is performed by a high-density plasma chemical vapor deposition process with a relatively high etching / deposition ratio. Then, a second stage of insulating layer deposition is performed using a high density plasma chemical vapor deposition process with a lower etch / deposition ratio to form an insulating layer filling the trenches on the substrate. After removing the insulating layer outside the trench, the mask layer and pad oxide layer are removed in sequence to form a shallow trench isolation structure.

Description

technical field [0001] The present invention relates to a manufacturing method of an electrically insulating (Electrically insulating) structure, and in particular to a manufacturing method of a shallow trench isolation (Shallow Trench Isolation, STI) structure. Background technique [0002] With the increasing integration of semiconductor devices, the design scale of the devices is shrinking day by day, and the electrical insulation structure in the device, such as the silicon oxide insulating layer, cannot be manufactured by Local Oxidation (LOCOS). One of the most widely used methods today is to manufacture electrical isolation structures by forming shallow trench isolation structures. [0003] Since the High Density Plasma Chemical Vapor Deposition (HDPCVD) method has two functions of "etching" and "deposition", the etching reaction of peeling off the deposit will also be carried out during the deposition, so that The high-density plasma chemical vapor deposition method...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/76
Inventor 刘婉懿张炳一
Owner MACRONIX INT CO LTD
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