Phase-locked loop circuit of eliminating self-shaking in signals received by control circuit

Abstract

PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, having a phase comparison circuit for producing a phase difference signal, which indicates the phase difference between the received signal and a fed-back output signal from the PLL circuit; having a loop filter for filtering the phase difference signal which is produced; having an oscillator, which is controlled by the filtered phase difference signal, for producing the output signal from the PLL circuit; with the loop filter having a nonlinear transfer function.

Description

technical field [0001] The present invention relates to a PLL circuit for eliminating self-jitter in a signal received by a control circuit, in particular in a signal sent by a clock and data recovery circuit (CDR) in a receiver. Background technique [0002] figure 1 An ADPLL circuit (ADPLL: All Digital Phase Locked Loop) is shown according to the prior art. The PLL circuit can be analog or digital. The PLL circuit is a phase locked loop and is used to synchronize the frequency and phase of two oscillations. In this case, the PLL circuit mainly includes: a phase comparison circuit for generating a phase difference signal and determining the phase difference between the received signal and the feedback output signal from the PLL circuit; a downlink loop filter for filtering the resulting phase difference signal; and an oscillator controlled by the filtered phase difference and generating the output signal of the PLL circuit. [0003] Figure 2a shows the prior art used in...

AI Technical Summary

Problems solved by technology

In this case, the frequency of the clock signal stabilized by the PLL circuit deviates from the frequency of the received data signal, and data loss may occur when transferring the received data to the data registers clocked by the stabilized clock signal

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