Phase-locked loop circuit of eliminating self-shaking in signals received by control circuit

Abstract

PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, having a phase comparison circuit for producing a phase difference signal, which indicates the phase difference between the received signal and a fed-back output signal from the PLL circuit; having a loop filter for filtering the phase difference signal which is produced; having an oscillator, which is controlled by the filtered phase difference signal, for producing the output signal from the PLL circuit; with the loop filter having a nonlinear transfer function.

Description

Technical field

[0001] The present invention relates to a PLL circuit for eliminating the self-jitter in the signal received by the control circuit, especially the self-jitter in the signal sent by the clock and data recovery circuit (CDR) in the receiver. Background technique

[0002] figure 1 An ADPLL circuit (ADPLL: All Digital Phase Locked Loop) is shown according to the prior art. The PLL circuit can be analog or digital. The PLL circuit is a phase-locked loop and is used to synchronize the frequency and phase of the two oscillations. In this case, the PLL circuit mainly includes: a phase comparison circuit for generating a phase difference signal and determining the phase difference between the received signal and the feedback output signal from the PLL circuit; a downstream loop filter for filtering The generated phase difference signal; and the oscillator, which is controlled by the filtered phase difference and generates the output signal of the PLL circuit.

[0003] F...

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