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Process comprising an internal memory configuration

A processor and auxiliary processor technology, applied in electrical digital data processing, instruments, memory systems, etc., can solve the problems of time loss, endangering safety, etc.

Inactive Publication Date: 2007-04-18
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, as already stated, this is at the cost of compromised security and lost time due to the transfer of operands between the external memory 360 and the computing unit 300

Method used

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  • Process comprising an internal memory configuration
  • Process comprising an internal memory configuration
  • Process comprising an internal memory configuration

Examples

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Embodiment Construction

[0020] Figure 1 shows an inventive processor. The processor comprises a computing unit 10, a register memory 12, an internal bus 14 between the register memory 12 and the computing unit 10, and a more internal bus 14' between the computing unit 10 and the register memory 12 In order to provide the results of the calculation unit to the register memory 12, a control unit 16 can control the operation of the calculation unit 10 and the operation of the register memory 12 through the control line, and an external bus 18 is used to communicate with peripheral devices, such as an input / output interface, another processor, etc., and a buffer memory configuration unit 20. The register memory configuration unit 20 can creatively configure the register memory 12 via a memory configuration circuit 22 .

[0021] As shown in FIG. 1, the register memory 12 is structured such that it has a memory portion 12a where the registers can be structured for the computing unit 10 and it has another...

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Abstract

A processor comprises an arithmetic unit (10) for processing operands, a register memory (12) for storing the operands using a register memory location, and a register memory configuration unit (20). The register memory configuration unit (20) is designed in order to configure the register memory in such a manner that a memory location (12a) in the register memory (12) is allocated to the operands and that a memory location (12b) in the register memory (12), which is not allocated to the operands, is provided for storing data other than the operands. In doing this, the number of operand transfers between an external bus and the arithmetic unit is reduced since as many operands as possible are stored in the register memory, whereas in the event that a portion of the register memory is not required for storing operands, this portion does not lie idle but is provided for storing other data so that the memory resources of the processor are always optimally used.

Description

technical field [0001] The present invention relates to computer internals and in particular to processor internals having a computing unit and a register memory. Background technique [0002] FIG. 3 shows a known processor internal structure in an example of a co-processor. The co-processor includes a calculation unit 300 , a register memory 310 and a control part 320 . The calculation unit 300 , the register memory 310 for the operation domain of the calculation unit and the control part 320 are completely configured on the coprocessor 330 . The coprocessor is connected to an external bus 350 via an internal connection bus 340 . An external memory 360 , a host CPU (not shown), and an input / output interface (not shown), etc. are also connected to the external bus 350 . [0003] The computing unit is connected to the register memory via an internal bus 370 . The control part 320 communicates with the register memory 310 or the computing unit 300 respectively, via control...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/318G06F9/38G06F9/34G09C1/00
CPCG06F9/30138
Inventor A·埃贝N·詹森
Owner INFINEON TECH AG
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