Display apparatus drive circuit having plurality of cascade connnected drive ics

Abstract

To prevent a timing shift of a clock and data supplied to a driver IC. A driver 1011 includes a phase adjustment circuit 201 for receiving via input terminals a clock and data outputted from a controller 103, latching received data with the clock adjusted to a 50-percent duty ratio, and outputting as phase-adjusted signals the data having the latched data further latched by synchronizing it with a delay clock having the duty-ratio-adjusted clock delayed by (pi / 2) and the clock of the 50-percent duty ratio.

Description

technical field [0001] The present invention relates to a display device driving circuit, in particular, the present invention relates to a display device driving circuit having a plurality of cascaded driver ICs (Integrated Circuits). Background technique [0002] In recent years, the size of display panels has been increasing, and a display device driving circuit for driving a display device having a plurality of cascaded driver ICs has attracted attention. [0003] For such driver ICs, usually, Figure 7 The driver IC shown is generally known as prior art (for example, see Patent Document 1). [0004] Figure 7 The illustrated driver IC 701 includes a phase adjustment circuit 702 , a data latch circuit 703 , a grayscale selection circuit 704 , and an output circuit 705 . [0005] The phase adjustment circuit 702 receives display data and a clock from an LCD controller not shown, performs phase adjustment, and then transfers the data to the next-stage driver IC, and also ...

AI Technical Summary

Problems solved by technology

As for the duty cycle of the data, there is no control over it, so that the duty cycle changes and causes the problem that the data cannot be latched correctly

In addition, phase adjustment among the enable signal, data, and clock signals is not performed, thereby causing a problem that data cannot be received correctly when data is received in response to the enable signal

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