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Data alignment circuit in receiving channel of billion Ethernet receiver

A Gigabit Ethernet, data alignment technology, applied in the direction of line transmission parts and so on

Inactive Publication Date: 2005-01-05
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At the same time, it is quite challenging to transmit 250Mbps signals bidirectionally and concurrently on four pairs of twisted pairs, and thus the problem to be solved by the present invention arises
[0005] Due to the differences in the four pairs of twisted pairs, the signals have different delays during transmission. The data sent by the sending end on the four pairs of twisted pairs at the same time may arrive at the receiving end at different times.

Method used

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  • Data alignment circuit in receiving channel of billion Ethernet receiver
  • Data alignment circuit in receiving channel of billion Ethernet receiver
  • Data alignment circuit in receiving channel of billion Ethernet receiver

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Embodiment Construction

[0021] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0022] The invention provides a method for aligning receiving channel data in a 1000BASE-T transceiver.

[0023] The present invention provides two schemes for data alignment. figure 1 The Deskew module 101 in belongs to the first kind of scheme, and it is composed of input data queue 201, decider 202, 203, 204, 205, n0 generator 206, conjecture sequence generator 207, serial-to-parallel converter 208, sequence matcher 209, 210, 211 and output multiplexers 212, 213, 214, and its structural block diagram is as follows image 3 shown.

[0024] image 3The middle input data queue (FIFO) 201 is made up of 405 D flip-flops, and its structure is as follows Figure 5 shown. These 405 D flip-flops form 4 FIFOs with a word width of 5, which are used as data buffers for the four channels of A, B, C and D respectively. The FIFO used for channel A has a depth of 15, and th...

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Abstract

This invention relates to a data align circuit in a giga Ether net receiver receiving channel composed of an input data array, a decider array, a 'no' generator, a guest array generator, a serial / parallel converter, an array match device and an output multipath selector, one connection way of which in the system is between the equalizer and Vilerbi decoder, the second way is to divide the module into a control part and a data channel part, the control part is connected after the equalizer, the data channel part is connected between the A / D converter and the equalizer, which aligns data on four pairs of twisted-pair lines in the receiving path so that the post decoding operates correctly.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to the circuit design of a data alignment module in a receiving channel of a Gigabit Ethernet (1000BASE-T) transceiver. Background technique [0002] In recent years, local area networks (LANs) have become increasingly mainstream for the local interconnection of personal computers, workstations, and servers. 10BASE-T was once the most common LAN technology. With the continuous increase of the amount of information exchange, a higher speed (larger bandwidth) LAN technology is objectively required. In this case, Fast Ethernet (100BASE-TX) appears. Fast Ethernet smoothly increases the network speed from 10Mbps to 100Mbps on the basis of 10BASE-T. However, with the increasing application of Fast Ethernet in servers and desktop systems, there is an urgent need to adopt higher-speed LAN technologies in backbone networks and server-level networks. [0003] Gigabi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B3/02
Inventor 任俊彦叶凡陈再敏王雪静刘爱林吴新华李宁
Owner FUDAN UNIV
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