Memory managing system and task controller in multitask system
A task control and multi-task technology, applied in the direction of program control design, instruments, sewing equipment, etc., can solve the problem of deteriorating interrupt response performance and achieve the effect of reducing the available amount
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no. 1 approach
[0026] figure 1 It is a block diagram showing a method of using a stack in a multitasking system according to the present invention. In terms of setting the location of the stack 107 that handles interrupts, the multitasking system is more efficient than figure 2 The conventional multitasking system shown is more distinctive.
[0027] exist figure 2 In the shown conventional multitasking system, three tasks 102, 104 and 106 and an interrupt handler 108 run on an operating system 109 (hereinafter referred to as OS). Stack areas 101, 103, 205, and 207 are independently prepared for tasks or programs. The task with the lowest priority among the three tasks is called the idle task 106 . When executing the idle task, it indicates a state in which the system has no task to process and an external interrupt is waiting to be entered.
[0028] exist figure 1 In the shown multitasking system according to the present invention, three tasks 102, 104 and 106 and an interrupt hand...
no. 2 approach
[0048] The multitasking system described in the first embodiment of the present invention can include Figure 10 It can also be implemented in the idle task of other processing shown in the flow chart, or it can only include Figure 9 Implemented in the idle task of the simple infinite loop shown. Figure 10 , as shown in step S1001, the idle task program executes a process of jumping the operation mode of the CPU to the low power consumption mode. Here, after the CPU jumps to the low power consumption mode, subsequent instructions are not executed until an interrupt is received. When an interrupt request enters the CPU and the low power consumption mode is released, the CPU returns to normal operation mode and executes Figure 7 OS interrupt input processing shown in the flowchart in .
[0049] The r0 register is used as a CPU register when the operation mode of the CPU transitions to the low power consumption mode. In this case, the value of the r0 register needs to be s...
no. 3 approach
[0057] The first embodiment and the second embodiment are described by paying attention to idle tasks. However, the same approach can be applied to normal tasks other than idle tasks when the CPU registers used by the tasks are identified with certainty. Also, the CPU registers used by a task are not statically determined. Even in this case, the method described in the second embodiment can be applied to CPU registers whose data can be overwritten as well as CPU registers whose data does not need to be overwritten by retaining information in variables of task processing or the like. Furthermore, when a high-level language such as C language is used, the method described in the second embodiment can be employed such that the compiler stores information related to CPU registers in the form of variables or SP difference information storage registers provided on the CPU.
[0058] Figure 13 It represents the task controller of the present invention for realizing the above-mentio...
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