Memory bandwidth control device
一种存储器带宽、控制装置的技术,应用在仪器、输入/输出到记录载体、电数字数据处理等方向,能够解决数据传输效率降低等问题
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[0017] With reference to accompanying drawing, preferred embodiment of the present invention will be described: (1) the circuit structure of memory bandwidth control device
[0018] refer to figure 1 , Reference numeral 1 designates the memory bandwidth control device of the present invention installed in the editing equipment, which transmits material data with hard disk drive (HDD) 60 through memory 80, memory 80 includes such as double data transfer rate-synchronous dynamic random access Memory (DDR-SDRAM).
[0019] The memory bandwidth control device 1 is structured with a field programmable gate array (FPGA), and the device is designed so that it passes through various input / output ports, such as the first serial data interface (SDI)-IN port 3, the second SDI- IN port 4, first SDI-OUT port 5, second SDI-OUT port 6, ENC / DEC port 7 and CPU port 12, with first to fourth devices 50 to 53 connected to I / O buffer 2, Encoder / decoder (ENC / DEC) 54 and CPU62, carry out the transm...
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