Unlock instant, AI-driven research and patent intelligence for your innovation.

Planarizing gate material to improve gate critical dimension in semiconductor devices

A technology of gate materials and semiconductors, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of mobility reduction device size, short channel effect, excessive leakage, etc.

Active Publication Date: 2005-12-21
ADVANCED MICRO DEVICES INC
View PDF0 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] For example, when the gate lengths of known planar metal-oxide-semiconductor field-effect transistors (MOSFETs) range below 100 nanometers, problems related to short-channel effects, such as excessive leakage between source and drain, become more and more difficult to overcome
In addition, mobility reduction degradation and some process issues also make it difficult for the size range of known MOSFETs to include smaller and smaller device sizes.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Planarizing gate material to improve gate critical dimension in semiconductor devices
  • Planarizing gate material to improve gate critical dimension in semiconductor devices
  • Planarizing gate material to improve gate critical dimension in semiconductor devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0040] In other embodiments, it is desirable to improve the etch profile in the fin structure of a FinFET. Figure 6A A cross-sectional view showing a typical etch profile of a fin structure 600 . Using a general poly etch process, the fin structure 600 can be formed on, for example, Figure 6A on the buried oxide layer 605 of the silicon-on-insulator structure shown in FIG. The fin structure 600 may include a silicon portion 610 , a silicon dioxide layer 620 , a silicon nitride layer 630 , and a photoresist mask layer 640 . Using a typical etch process to form the fin structure 600 can result in Figure 6A The "large footing" shown in , where the base of the silicon portion 610 increases the width of its base. This pedestal enables different channel dimensions in the resulting FinFET.

[0041] Figure 6B A cross-sectional view showing the improved vertical etch profile of the fin structure 600 . Using a T-type gate or a Notch gate etch approach, the fin structure 600 ca...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Smallest sizeaaaaaaaaaa
Login to View More

Abstract

A method of manufacturing a semiconductor device (100), including forming a fin structure (210) on an insulating layer (120). The fin structure (210) may include side surfaces and an upper surface. The method may also include depositing a layer of gate material (320) on the fin structure (210) and planarizing the deposited layer of gate material (320). An anti-reflection coating (520) may be deposited on the planarized gate material layer (320), and gates are formed from the planarized gate material layer (320) through the anti-reflection coating (520) structure (510).

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, in particular to those suitable for double-gate devices. Background technique [0002] Due to the increasing demand for high density and performance related to VLSI, semiconductor devices require their design dimensions (such as gate length below 100 nm), high reliability, and increased manufacturing yield. Scaling design dimensions below 100 nanometers is challenging the limits of existing method technologies. [0003] For example, when the gate lengths of known planar metal-oxide-semiconductor field-effect transistors (MOSFETs) range below 100 nanometers, problems related to short-channel effects, such as excessive leakage between source and drain, become increasingly difficult to overcome. In addition, mobility reduction degradation and some process issues also make it difficult for the size range of known MOSFETs to include smaller and ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/336H01L29/423
CPCH01L29/42384H01L29/66795H01L29/785H01L29/7853H01L21/18
Inventor S·S·艾哈迈德C·E·塔贝里H·王B·俞
Owner ADVANCED MICRO DEVICES INC