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Microprocessor including cache memory supporting multiple accesses per cycle

A high-speed cache and microprocessor technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as inability to process access actions

Inactive Publication Date: 2006-01-04
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Some conventional processors cannot handle other accesses to L1 and L2 caches during the time these cache lines are "swapped"

Method used

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  • Microprocessor including cache memory supporting multiple accesses per cycle
  • Microprocessor including cache memory supporting multiple accesses per cycle
  • Microprocessor including cache memory supporting multiple accesses per cycle

Examples

Experimental program
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Embodiment Construction

[0037] now refer to figure 1 , a block diagram of an embodiment of the microprocessor 100 is shown in the figure. Microprocessor 100 is configured to execute instructions stored in system memory (not shown). Many of these instructions operate on data stored in system memory. It must be noted that system memory may actually be distributed throughout the computer system and may be accessed by one or more microprocessors such as microprocessor 100 . In one embodiment, microprocessor 100 is an example of a microprocessor equipped with an x86 system architecture, such as an Athlon TM microprocessor. However, embodiments including other forms of microprocessors are also contemplated.

[0038]In the illustrated embodiment, microprocessor 100 includes a first level one (L1) cache and a second level one (L1) cache: an instruction cache 101A and a data cache 101B. Depending on its application, the first level cache can be a consolidated cache or separate caches. For the sake of co...

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PUM

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Abstract

A microprocessor (100) including a level two cache memory (200) which supports multiple accesses per cycle. The microprocessor (100) includes an execution unit (124) coupled to a cache memory subsystem which includes a cache memory (200) coupled to a plurality of buses (240). The cache memory (200) includes a plurality of independently accessible storage blocks (220). The buses (240) may be coupled to convey a plurality of cache access requests to each of the storage blocks (220). In response to the plurality of cache access requests being conveyed on the plurality of cache buses (240), different ones of the storage blocks (220) are concurrently accessible.

Description

technical field [0001] The present invention relates to the field of microprocessors, and more specifically, to cache memory management within microprocessors. Background technique [0002] A typical computer system may contain one or more microprocessors, which may be coupled to one or more system memories. These microprocessors run code and perform operations on data stored in system memory. Note that the term "processor" is used herein synonymously with microprocessor. To facilitate the retrieval and storage of instructions and data, processors typically employ some form of memory system. Additionally, in order to speed up system memory access operations, the memory system may include one or more cache memories. For example, some microprocessors may have one or more levels of cache memory. A typical microprocessor uses a first-level cache (L1 cache) and a second-level cache (L2 cache), while some newer processors may also use a third-level cache (L3 cache). Many olde...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0851G06F12/08G06F12/0848G06F12/1045
Inventor M·阿尔叙
Owner ADVANCED MICRO DEVICES INC