Mechanism for handling explicit writeback in a cache coherent multi-node architecture

Abstract

A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

Description

RELATED APPLICATIONS [0001] This application is a continuation of U.S. application Ser. No. 10 / 896,151 filed on Jul. 20, 2004, which is a continuation of U.S. application Ser. No. 09 / 823,791, filed on Mar. 31, 2001, entitled “Mechanism for Handling Explicit Writeback in a Cache Coherent Multi-Node Architecture.”BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The invention relates to communications between integrated circuits and more specifically to data transfer and coherency in a multi-node or multi-processor system. [0004] 2. Description of the Related Art [0005] Processors and caches have existed since shortly after the advent of the computer. However, the move to using multiple processors has posed new challenges. Previously, data existed in one place (memory for example) and might be copied into one other place (a cache for example). Keeping data coherent between the two possible locations for the data was a relatively simple problem. Utilizing multiple pro...

AI Technical Summary

Benefits of technology

"The invention is about a mechanism for handling conflicts between processors in a multi-processor system. These conflicts can occur when multiple processors need to read and write data at the same time. The mechanism uses a scalability port to compare the addresses of reads and writes and make decisions on whether to stall the read or the write based on factors like priority and nature of the requests. This results in a predictable outcome and allows users to adapt their use of the system to the predictable result. Overall, the invention reduces conflicts between processors and improves the efficiency and reliability of multi-processor systems."

Problems solved by technology

However, the move to using multiple processors has posed new challenges.

Keeping data coherent between the two possible locations for the data was a relatively simple problem.

If two copies of the data exist, or one copy exists aside from the original, some potential for a conflict in data exists in a multi-processor system.

The corrupted data may result when the read retrieval of the updated data.

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