Circuit and method to find wordline-bitline shorts in a dram

Abstract

Method and apparatus for testing for a short between a wordline being tested and a bitline in a memory device. The method includes applying a first voltage to the bitline using a first voltage source and applying a second voltage to the wordline being tested using a second voltage source. The method further includes disconnecting the wordline being tested from the second voltage source; and after disconnecting the wordline being tested from the second voltage source, activating the wordline being tested, thereby connecting the wordline being tested to a wordline power supply line. A determination is made of whether a voltage of the wordline power supply line indicates a short between the wordline being tested and the bitline. The determination is based on the voltage of the wordline power supply line relative to the first voltage and the second voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is related to U.S. patent application Ser. No. 11 / 240,981, Attorney Docket No. INFN / EH0181, filed Sep. 29, 2005, by Martin Versen et al., published as US2007 / 0070745A1, entitled REDUNDANT WORDLINE DEACTIVATION SCHEME. This related patent application is herein incorporated by reference in its entirety.BACKGROUND OF THE INVENTION[0002]Many modern electronic devices contain digital memory (e.g., a dynamic random access memory, DRAM). Each memory may be used to store information for a digital device. Users of such electronic devices typically desire large amounts of memory in a small package. Where the electronic devices are portable (e.g., battery powered), users may also desire electronic devices which do not consume as much power and therefore have a longer battery life. Thus, manufacturers of electronic devices typically desire small, high density memories with low power consumption.[0003]To meet the demand for small, hig...

AI Technical Summary

Problems solved by technology

Users of such electronic devices typically desire large amounts of memory in a small package.

However, as the size of features in a memory chip shrinks and as the memory density of a memory chip increases, errors in the manufacturing process may cause more defective memories at a high cost to the manufacturer.

Where a wordline and bitline are shorted, the memory cell located at the junction of the wordline and bitline may, in some cases, not be accessible, thereby resulting in a defective memory cell and defective memory device.

While repairing a defective wordline may prevent a memory device from losing data, the defective wordline may still remain shorted to a bitline.

In some cases, where a defective wordline is shorted to a bitline, current may flow between the defective wordline and the bitline, thereby increasing the power consumption of the memory device.

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