Methods of forming diffusion breaks on integrated circuit products comprised of finfet devices and the resulting products

Abstract

One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming diffusion breaks on integrated circuit (IC) products comprised of FinFET devices and the resulting IC products.[0003]2. Description of the Related Art[0004]In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source / drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit product...

AI Technical Summary

Benefits of technology

The present patent discloses methods for forming diffusion breaks on IC products comprised of FinFET devices. The methods involve the removal of sacrificial gate structures to create a cavity which can expose the fin and leave the active gate structures intact. An insulating material is then filled into the cavity to create a replacement gate cavity for the active gates. A replacement gate structure is then formed in each of the replacement gate cavities. The technical effects of the patent text include improved performance, reliability, and stability of IC products containing diffusion breaks.

Problems solved by technology

However, the formation of such trenches consumes very valuable plot space on the substrate 12.

Moreover, in some applications, such as those integrated circuit products employing FinFET transistor devices, as device sizes have decreased, and packing densities have increased, it is sometimes difficult to form the desired isolation region made of an insulating material.

Unfortunately, producing such a tucked fin arrangement requires the use of two dummy gate lines.

Having two dummy gate lines at each cell boundary of an integrated circuit product consumes valuable plot space and reduces cell efficiency.

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