Determining Transient Error Functional Masking And Propagation Probabilities

a transient error and probabilistic technology, applied in the field of microelectronic design, can solve problems such as memory glitches, value of output of the combo-gate to be flipped, and disturb an expected functionality of the devi

a transient error and probabilistic technology, applied in the field of microelectronic design, can solve problems such as memory glitches, value of output of the combo-gate to be flipped, and disturb an expected functionality of the devi

US20160370429A9Active Publication Date: 2016-12-22OPTIMA DESIGN AUTOMATION
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  • Determining Transient Error Functional Masking And Propagation Probabilities
  • Determining Transient Error Functional Masking And Propagation Probabilities
  • Determining Transient Error Functional Masking And Propagation Probabilities

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Embodiment Construction

[0018]In the present disclosure the term “Transient Error” refers to a logical glitch on the output of a single combo-gate, (e.g., AND-gate, OR-Gate, XOR-Gate, MUX-Gate, or the like) or other kinds of gates. This glitch is temporary value change from 0 to 1 or 1 to 0 for a short period of time (sub-cycle). This glitch may be caused by electromagnetic radiation striking the combo-gate in the digital circuit, such as, a microprocessor, or the like. The bit flip may be a result of the free charge created by ionization in or close to a gate. The TE may occur spontaneously and unexpectedly due to an environment in which the circuit is operated.

[0019]TE may propagate through the combo-logic influenced by the said gate and get sampled (or latched) at one or more memory elements (flip-flop, latch, register or the like). Error Propagated (EP) is when a TE is inflicted at certain gate and the wrong value has propagated to the input of memory elements, and the memory element may sample the wro...

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Abstract

A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]The present application claims the benefit of Provisional Patent Application U.S. 62 / 106,305, filed 22 Jan. 2015, and is a continuation in part of patent application U.S. Ser. No. 14 / 601,312 filed Jan. 21, 2015 which is the non-provisional if Provisional Patent Application U.S. 61 / 941,125 filed on Feb. 18, 2014, and a continuation in part of patent application U.S. Ser. No. 14 / 624,603 filed on Feb. 18, 2015, all of which are hereby incorporated in reference in their entirety for all purposes without giving rise to disavowment.TECHNICAL FIELD[0002]The present disclosure relates to microelectronic design in general, and to designing circuit that reduce a risk of soft error as a result of a Transient Error, in particular.BACKGROUND[0003]Transient Error (TE) is when a combinatorial-gate (combo-gate) inside an electronic chip has a glitch on its output, for any reason, one of them is radiation related to cosmic ray and nuclear particles coming ...

Claims

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Application Information

Patent Timeline
22 Dec 2016
Publication
US20160370429A9
IPC
G01R31/317; G01R31/3177
CPC
G01R31/3177; G01R31/31703; G06F30/33; G06F30/20
Inventors
MAZZAWI, JAMIL RAJA; MOUALLEM, AYMAN KAMIL