Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. The top interposer is electrically connected to the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are present between the package substrate and the top interposer.

Description

BACKGROUNDField of Disclosure[0001]The present disclosure relates to a semiconductor package.Description of Related Art[0002]Integrated circuit (IC) product technology incorporates a number of heterogeneous functions such as central processing unit (CPU) logic, graphics functions, cache memory and other system functions to create integrated system-on-chip (SOC) or system-in-chip (SIC) designs. The SOC / SIC designs may lower product design complexity and number of components for each product. ICs are miniature devices with tiny contact pads that are connected to other IC or non-IC components. The connection to other components is facilitated by substrates such as printed circuit boards (PCBs). However, products may have required a system board using separate packages for the different functions, which may increase a system board area, power loss, and cost of an integrated solution.SUMMARY[0003]An aspect of the present disclosure is to provide a semiconductor package including a packag...

AI Technical Summary

Benefits of technology

The present patent provides a semiconductor package and a method for manufacturing it. The package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first and second semiconductor chips are adhered to the package substrate and the top interposer. The top interposer includes a core and at least one trace layer that interconnects the first and second semiconductor chips. The semiconductor package may also include a bottom interposer and a third semiconductor chip. The technical effects of this patent include improved signal integrity, reduced latency, and reduced power consumption.

Problems solved by technology

However, products may have required a system board using separate packages for the different functions, which may increase a system board area, power loss, and cost of an integrated solution.

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