Apparatus and method for decoding LDPC code based on prototype parity check matrixes

Abstract

Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present invention claims priority of Korean Patent Application No. 10-2007-0131487, filed on Dec. 14, 2007, which is incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes; and, more particularly, to an apparatus and method for decoding a LDPC code based on prototype parity check matrixes which performs decoding at high-speed while reducing complexity by sequentially performing a partial parallel process on the parity check matrix based on multiple prototype parity check matrixes determined according to a parallelization figure in decoding an input bit based on the parity check matrix, to thereby support the length and the bit rate of diverse code words.[0004]This work was supported by the IT R&D program for MIC / IITA [2006-S-002-02, “IMT-Advanced...

AI Technical Summary

Benefits of technology

[0019]An embodiment of the present invention is directed to providing an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes which performs decoding at high-speed while reducing complexity by sequentially performing a partial parallel process on the parity check matrix according to multiple prototype parity check matrixes determined based on a parallelization figure in decoding an input bit based on the parity check matrix, to thereby support the length and the bit rate of diverse code words.

Problems solved by technology

However, the serial or partial parallel processing method has a shortcoming that high-speed decoding cannot be supported.

On the other hand, the information shortening technique or punching technique has a problem that the error correction performance of the LDPC code may be deteriorated by randomly applying the information shortening technique or the parity punching technique.

However, the decoding method of the conventional parallel processing method has a problem that a process time is delayed by increase of calculation quantity and complexity due to random and complex connection between the variable node and the check node.

In particular, there is a problem that it is difficult to adaptively correspond to the change of the length and the bit rate of the code word since the calculation quantity and the complexity increases to support the diverse code word lengths and the diverse bit rates in the decoding method of the conventional parallel processing method.

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