Regulating board of static var compensator based on floating point DSP and FPGA

Abstract

The invention relates to a static reactive power compensator adjusting plate which is formed by a 32-bit floating point digital processing chip (DSP) and super large on-site programmable logic gate array (FPGA). It is mainly formed by 32-bit floating point DSP and FPGA. It also comprises: 40 paths 14-bit analogue / digital conversion chip, a digital phase-locked loop PLL, a CAN controller and 8 paths photo isolating input-output circuit and so on. The circuit integer on a 4 layers block body to achieve the CPU bus inside the circuit plate. The circuit plate adopts 4 layers wiring, crystal art, meter-floating circuit, European type connecter and electromagnetic anti-interference to achieve the electromagnetic compatible standard EMC fast transient 4 standard on line program.

Description

technical field [0001] The invention relates to a static var compensator (SVC) adjustment unit in power systems and power electronics technology, in particular to a combination of a 32-bit floating-point digital processing chip (DSP) and an ultra-large-scale field programmable logic gate array (FPGA). The finished static var compensator regulating board. Background technique [0002] With the implementation of my country's "West to East Power Transmission" strategy and the expansion of the scale of the interconnected grid, the problem of voltage stability is particularly prominent. The main problem of the super-large load center formed in the southeast coast of my country is that the dynamic reactive power support is increasingly insufficient. In the past two decades, large-scale power outages caused by voltage stability and voltage collapse have occurred in many parts of the world, and voltage collapse accidents have also occurred many times in my country. The use of stat...

AI Technical Summary

Problems solved by technology

These technical difficulties determine that the development of the SVC regulating board is very difficult

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